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GATE EC Op-amp Circuits questions

Practise Op-amp Circuits questions for GATE EC. Explore official PYQs and original topic-wise quizzes, check answers and view available solutions. Free, no sign-in.

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Official PYQ2017Analog CircuitsOp-amp CircuitsNAT · 2 marks
In the voltage reference circuit shown in the figure, the op-amp is ideal and the transistors Q1,Q2,…,Q32Q_1, Q_2, \dots ,Q_{32} are identical in all respects and have infinitely large values of common-emitter current gain (β)(\beta). The collector current (Ic)(Ic) of the transistors is related to their base-emitter voltage (VBEV_{BE}) by the relation …
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 1 mark
The following signal ViV_i of peak voltage 8 V8 \: V is applied to the non-inverting terminal of an ideal Op-amp.The transistor has VEE=0.7 VV_{EE}=0.7 \: V, β=100; VLED=1.5 V\beta=100; \: V_{LED}=1.5 \: V, VCC=10 VV_{CC}=10 \: V and –VCC=–10 V– V_{CC}= – 10 \:V. The number of times the LED glows is ________
Official PYQ2016Analog CircuitsOp-amp CircuitsMCQ · 1 mark
Consider the oscillator circuit shown in the figure. The function of the network (shown in dotted lines) consisting of the 100 kΩ100 \: k \Omega resistor in series with the two diodes connected back-to-back is to:
Official PYQ2016Analog CircuitsOp-amp CircuitsMCQ · 1 mark
The block diagram of a frequency synthesizer consisting of a Phase Locked Loop (PLL) and a divide-by-NN counter (comprising ÷2,÷4,÷8,÷16\div 2, \div 4, \div 8, \div 16 outputs) is sketched below. The synthesizer is excited with a 55 kHz signal (Input 11). The free-running frequency of the PLL is set to 2020 kHz. Assume that the commutator switch makes …
Official PYQ2016Analog CircuitsOp-amp CircuitsMCQ · 1 mark
The output of the combinational circuit given below is
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 1 mark
A superheterodyne receiver operates in the frequency range of 5858 MHz – 6868 MHz. The intermediate frequency fIFf_{IF} and local oscillator frequency fLOf_{LO} are chosen such that fIF≤fLOf_{IF} \leq f_{LO}. It is required that the image frequencies fall outside the 5858 MHz – 6868 MHz band. The minimum required fIFf_{IF} (in MHz) is _________
Official PYQ2016Analog CircuitsOp-amp CircuitsMCQ · 2 marks
A network consisting of a finite number of linear resistor (R), inductor (L), and capacitor (C) elements, connected all in series or all in parallel, is excited with a source of the form ∑k=13akcos⁡(kω0t),where  ak≠0,ω0≠0\sum_{k=1}^{3} a_k\cos(k\omega_0t) ,\text{where } \thinspace a_k\neq 0, \omega_0\neq0 The source has nonzero impedance. Which one of the following is a possible form of …
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 2 marks
An ideal opamp has voltage sources V1,V3,V5,…,VN−1V_1, V_3, V_5, \dots, V_{N-1} connected to the non-inverting input and V2,V4,V6,…,VNV_2, V_4, V_6, \dots, V_N connected to the inverting input as shown in the figure below (+VCC=15(+V_{CC}= 15 volt, –VCC=–15– V_{CC} = – 15 volt). The voltages V1,V2,V3,V4,V5,V6,…V_1, V_2, V_3, V_4, V_5, V_6, \dots are 1,−1/2,1/3,−1/4,1/5,−1/6,…1, -1/2, 1/3, -1/4, 1/5, -1/6, \dots volt, …
Official PYQ2016Analog CircuitsOp-amp CircuitsMCQ · 1 mark
The switch has been in position 11 for a long time and abruptly changes to position 22 at t=0t = 0. If time tt is in seconds, the capacitor voltage VCV_{C} (in volts) for t>0t > 0 is given by
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 2 marks
An opamp has a finite open loop voltage gain of 100100. Its input offset voltage Vios(=+5mV)V_{ios}(=+5mV) is modeled as shown in the circuit below. The amplifier is ideal in all other respects. VinputV_{\text{input}} is 25 mV25 \: mV. The output voltage (in millivolts) is _________
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 2 marks
In the feedback system shown below G(s)=1(s2+2s)G\left ( s \right )=\frac{1}{\left ( s^{2}+2s \right )}. The step response of the closed-loop system should have minimum settling time and have no overshoot. The required value of gain kk to achieve this is __________
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 2 marks
In the feedback system shown below G(s)=1(s+1)(s+2)(s+3).G\left ( s \right )=\frac{1}{\left ( s+1 \right )\left (s+2 \right )\left ( s+3 \right )}. The positive value of kk for which the gain margin of the loop is exactly 00 dB and the phase margin of the loop is exactly zero degree is _________
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 1 mark
In the astable multivibrator circuit shown in the figure, the frequency of oscillation (in kHz) at the output pin 33 is _______
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 1 mark
For a superheterodyne receiver, the intermediate frequency is 15 MHz15\ MHz and the local oscillator frequency is 3.5 GHz3.5\ GHz. If the frequency of the received signal is greater than the local oscillator frequency, then the image frequency (in MHzMHz) is _______
Official PYQ2015Analog CircuitsOp-amp CircuitsNAT · 2 marks
In the circuit shown, assume that the opamp is ideal. The bridge output voltage V0V_0 (in mV) for δ=0.05\delta=0.05 is __________
Official PYQ2015Analog CircuitsOp-amp CircuitsMCQ · 2 marks
The circuit shown in the figure has an ideal opamp. The oscillation frequency and the condition to sustain the oscillations, respectively, are
Official PYQ2015Analog CircuitsOp-amp CircuitsNAT · 1 mark
In the circuit shown, V0=V0AV_{0} = V_{0A} for switch SWSW in position AA and V0=V0BV_{0} = V_{0B} for SWSW in position BB. Assume that the opamp is ideal. The value of V0BV0A\dfrac{V_{0B}}{V_{0A}} is ___________.
Official PYQ2015Analog CircuitsOp-amp CircuitsNAT · 1 mark
In the bistable circuit shown, the ideal opamp has saturation levels of ± 5 V.\pm\: 5\: V. The value of R1(in kΩ)R_{1} \text{(in}\: k\Omega) that gives a hysteresis width of 500 mV500\: mV is ________.
Official PYQ2015Analog CircuitsOp-amp CircuitsNAT · 2 marks
Assuming that the opamp in the circuit shown below is ideal, the output voltage ܸVoV_{o} (in volts) is________.
Official PYQ2015Analog CircuitsOp-amp CircuitsNAT · 2 marks
For the voltage regulator circuit shown, the input voltage (Vin)(V_{in}) is 20V±20%20 V \pm 20\% and the regulated output voltage (Vout)(V_{out}) is 10 V.10\: V. Assume the opamp to be ideal. For a load RLR_L drawing 200 mA,200\: mA, the maximum power dissipation in Q1 (in Watts)Q_{1}\:\text{(in Watts)} is ________.