GATE EC Data Converters questions

A $4$-bit weighted-resistor DAC with inputs $b_{3}, b_{2}, b_{1}$, and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ' $l$ ' and open otherwise. When the input $b_{3} b_{2} b_{1} b_{0}$ changes from $1110$ to $1101$, the magnitude of the change in the …

A $10$-bit analog-to-digital converter (ADC) has a sampling frequency of $1\: \mathrm{MHz}$ and a full scale voltage of $3.3 \: \mathrm{V}$. For an input sinusoidal signal with frequency $500 \: \mathrm{kHz}$ , the maximum SNR (in $\mathrm{dB}$ , rounded off to two decimal places) and the data rate (in $\mathrm{Mbps}$) at the output of the ADC …

​​​​​A full scale sinusoidal signal is applied to a $10$ -bit $\mathrm{ADC}$. The fundamental signal component in the $\mathrm{ADC}$ output has a normalized power of $1 \mathrm{~W}$, and the total noise and distortion normalized power is $10 \mu \mathrm{W}$. The effective number of bits (rounded off to the nearest integer) of the $\mathrm{ADC}$ …

The signal-to-noise ratio $\mathrm{SNR}$ of an $\mathrm{ADC}$ with a full-scale sinusoidal input is given to be $61.96 \mathrm{~dB}$. The resolution of the $\mathrm{ADC}$ is_____________bits (rounded off to the nearest integer).

A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of $1 \; \mu \mathrm{s}$. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of $1 \mathrm{~V}$ with $12$-bit accuracy is ___________ $\mu \mathrm{s}$ (rounded off to two decimal places).

An $8$-bit unipolar (all analog output values are positive) digital-to-analog converter $\text{(DAC)}$ has a full-scale voltage range from $0\; V$ to $7.68\:V$. If the digital input code is $10010110$ (the leftmost bit is $\text{MSB}$), then the analog output voltage of the $\text{DAC}$ (rounded off to one decimal place) is ___________ $V$.

A $10$-bit D/A converter is calibrated over the full range from $0$ to $10$ V. If the input to the D/A converter is $13 \:A$ (in hex), the output ( rounded off to three decimal places) is __________ $V$.

In an $N$ bit flash ADC, the analog voltage is fed simultaneously to $2^{N}-1$ comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source $V_{in}$ (whose output is being converted to digital format) has a source resistance of $75 \: \Omega$ as shown in the circuit …

Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog value (in Volts) corresponding to the digital signal $1111$ is _________

For a given sample-and-hold circuit, if the value of the hold capacitor is increased, then

Statement for Linked Answer Questions 83a and 83b: Asymmetric three-level midtread quantizer is to be designed assuming equiprobable occurence of all quantization levels. If the probability density function is divided into three regions as shown in the figure, the value of a in the figure is

The minimum number of comparators required to build an $8$ bit flash ADC is

A sinusoidal signal with peak-to-peak amplitude of $1.536 \mathrm{~V}$ is quantized into $128$ levels using a mid-rise uniform quantizer. The quantization-noise power is

The number of comparators required in a $3$-bit comparator type ADC is

The number of comparators in a $4$ bit flash $\text{ADC}$ is

An $8$ bit successive approximation analog to digital converter has full scale reading of $2.55 \mathrm{~V}$ and its conversion time for an analog input of $1 \mathrm{~V}$ is $20 \; \mu \mathrm{s}$. The conversion time for a $2 \mathrm{~V}$ input will be

For the $4$ bit $\text{DAC}$ shown, the output voltage $v_{0}$ is

The resolution of a $4$ - bit counting $\text{ADC}$ is $0.5$ volts. For an analog input of $6.6$ volts, the digital output of the $\text{ADC}$ will be

The advantage of using a dual slope $\text{ADC}$ in a digital voltmeter is that

A $12$ – bit $\text{ADC}$ is operating with a $1 \; \mu \; \mathrm{sec}$ clock period and the total conversion time is seen to be $14 \; \mu \;\mathrm{sec}$. The $\text{ADC}$ must be of the