Official PYQ · 2005Set 1 · Q83Data ConvertersMCQ1 mark

GATE EC 2005 Set 1 Q83 — Data Converters

Statement for Linked Answer Questions 83a and 83b:
Asymmetric three-level midtread quantizer is to be designed assuming equiprobable occurence of all quantization levels.

If the probability density function is divided into three regions as shown in the figure, the value of a in the figure is

View answer

Answer: B

Worked explanation not available yet.

Free practice · Your answers on this page are not saved.

Published 10 Oct 2026

Report a correction

GATE EC · 2025Data Converters
A $4$ -bit weighted-resistor DAC with inputs $b_{3}, b_{2}, b_{1}$ , and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ' $l$ ' and open otherwise. When the input $b_{3} b_{2} b_{1} b_{0}$ changes from $1110$ to $1101$ , the magnitude of the change in the …
NAT · 1 mark
GATE EC · 2025Data Converters
A $10$ -bit analog-to-digital converter (ADC) has a sampling frequency of $1\: \mathrm{MHz}$ and a full scale voltage of $3.3 \: \mathrm{V}$ . For an input sinusoidal signal with frequency $500 \: \mathrm{kHz}$ , the maximum SNR (in $\mathrm{dB}$ , rounded off to two decimal places) and the data rate (in $\mathrm{Mbps}$ ) at the output of the ADC …
MCQ · 2 marks
GATE EC · 2024Data Converters
A full scale sinusoidal signal is applied to a $10$ -bit $\mathrm{ADC}$ . The fundamental signal component in the $\mathrm{ADC}$ output has a normalized power of $1 \mathrm{~W}$ , and the total noise and distortion normalized power is $10 \mu \mathrm{W}$ . The effective number of bits (rounded off to the nearest integer) of the $\mathrm{ADC}$ …
MCQ · 2 marks
GATE EC · 2023Data Converters
The signal-to-noise ratio $\mathrm{SNR}$ of an $\mathrm{ADC}$ with a full-scale sinusoidal input is given to be $61.96 \mathrm{~dB}$ . The resolution of the $\mathrm{ADC}$ is_____________bits (rounded off to the nearest integer).
NAT · 1 mark
GATE EC · 2023Data Converters
A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of $1 \; \mu \mathrm{s}$ . The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of $1 \mathrm{~V}$ with $12$ -bit accuracy is ___________ $\mu \mathrm{s}$ (rounded off to two decimal places).
NAT · 2 marks
GATE EC · 2021Data Converters
An $8$ -bit unipolar (all analog output values are positive) digital-to-analog converter $\text{(DAC)}$ has a full-scale voltage range from $0\; V$ to $7.68\:V$ . If the digital input code is $10010110$ (the leftmost bit is $\text{MSB}$ ), then the analog output voltage of the $\text{DAC}$ (rounded off to one decimal place) is ___________ $V$ .
NAT · 1 mark

Browse this topic

More Data Converters questions

GATE EC 2005 Set 1 Q83 — Data Converters

Related questions