GATE EC Combinatorial Circuits questions

A function $F(A, B, C)$ defined by three Boolean variables $\text{A, B and C}$ when expressed as sum of products is given by $$F=\overline{A}\:.\overline{B}\:.\overline{C}+\overline{A}\:.B\:.\overline{C}+A\:.\overline{B}\:.\overline{C}$$ where, $\overline{A}\:,\overline{B}\:,and\:\overline{C}$ are the complements of the respective variables. The …

A four-variable Boolean function is realized using $4\times 1$ multiplexers as shown in the figure. The minimized expression for $\text{F(U,V,W,X)}$ is

A junction is made between $p^{-Si}$ with doping density $N_{A1}=10^{15}cm^{-3}$ and $p^{Si}$ with doping density $N_{A2}=10^{17}cm^{-3}.$ Given: Boltzmann constant $k=1.38\times 10^{-23}J\cdot K^{-1},$ electronic charge $q=1.6\times 10^{-19}C$. Assume $\text{100}\%$ acceptor ionization. At room temperature $\left ( T=300 K \right ),$ the …

The logic gates shown in the digital circuit below use strong pull-down $\text{nMOS}$ transistors for LOW logic level at the outputs. When the pull-downs are off, high-value resistors set the output logic levels to HIGH (i.e. the pull-ups are weak). Note that some nodes are intentionally shorted to implement “wired logic”. Such shorted nodes will be HIGH …

Which one of the following gives the simplified sum of products expression for the Boolean function $F=m_{0}+m_{2}+m_{3}+m_{5}$, where $m_{0},m_{2},m_{3}$ and $m_{5}$ are minterms corresponding to the inputs $A,B$ and $C$ with $A$ as the $MSB$ and $C$ as the $LSB$?

For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is

Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is

Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume all the inputs to the $4$-bit adder are initially reset to $0$. Figure I Figure II At $t = 0$, the …

A programmable logic array (PLA) is shown in the figure. The Boolean function $F$ implemented is

A small percentage of impurity is added to an intrinsic semiconductor at $300 \: K$. Which one of the following statements is true for the energy band diagram shown in the following figure?

Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): Which of the above statements are INCORRECT? P and Q P and S Q and R R and S

The functionality implemented by the circuit below is

A $4:1$ multiplexer is to be used for generating the output carry of a full adder. $A$ and $B$ are the bits to be added while $C_{in}$ is the input carry and $C_{out}$ is the output carry. $A$ and $B$ are to be used as the select bits with $A$ being the more significant select bit. Which one of the following statements correctly describes the …

The $I-V$ characteristics of three types of diodes at the room temperature, made of semiconductors $X, Y$ and $Z$, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If $E_{gX}$,$E_{gY}$ and $E_{gZ}$ are the band gaps of $X, Y$ and $Z$, respectively, then

The logic functionality realized by the circuit shown below is

The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is

Following is the K-map of a Boolean function of five variables $P,Q,R,S$ and $X$. The minimum sum-of-product (SOP) expression for the function is

A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is ___________

The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ converted into the canonical product of sum (POS) form is

A $3$-input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M(\overline{M(a,b,c)}, M(a,b,\overline{c}),c)$?