GATE EC Electronic Devices questions

The

\text{RC}

circuit shown below has a variable resistance

R(t)

given by the following expression:

R(t)=R_{0}\left(1-\frac{t}{T}\right) \text{for} \:\: 0 \leq t < T

where

R_{0}=1\: \Omega,

and

C=1\:F.

We are also given that

T=3\: R_{0}C

and the source voltage is

V_{s}=1\: V.

If the current at time

t=0

is

1\: A,

then …

In an ideal

pn

junction with an ideality factor of

1

at

T=300\:K,

the magnitude of the reverse-bias voltage required to reach

75\%

of its reverse saturation current, rounded off to

2

decimal places, is ______

mV.

[k=1.38 \times 10^{-23} JK^{-1}, h=6.625 \times 10^{-34} J-s, q=1.602 \times 10^{-19}C]

Consider a long-channel MOSFET with a channel length

1\:\mu m

and width

10\: \mu m.

The device parameters are acceptor concentration

N_{A}=5 \times 10^{16}\: cm^{-3},

electron mobility

\mu_{n}=800\: cm^{2}/V-s,

oxide capacitance/area

C_{ox}=3.45 \times 10^{-7}\:F/cm^{2},

threshold voltage

V_{T}=0.7\:V.

The drain saturation current …

In the circuit shown.

V_{s}

is a

10\:V

square wave of period,

T=4\: ms

with

R=500\: \Omega

and

C= 10\:\mu F.

The capacitor is initially uncharged at

t=0,

and the diode is assumed to be ideal. The voltage across the capacitor

(V_{c})

at

3\:ms

is equal to _____ volts (rounded off to one decimal place)

A CMOS inverter, designed to have a mid-point voltage

V_{1}

equal to half of

V_{dd}.

as shown in the figure, has the following parameters:

V_{dd}=3V

\mu_{n} C_{ox}=100\: \mu A/V^{2}; V_{tn}=0.7\:V

for

\text{nMOS}

\mu_{p} C_{ox}=40\: \mu A/V^{2}; \mid V_{tp} \mid=0.9\:V

for

\text{pMOS}

The ration of

\left(\frac{W}{L}\right)_{n}

…

In the circuit shown, the threshold voltages of the

pMOS\:\: (|V_{tp}|)

and

nMOS\:\: (V_{tn})

transistors are both equal to

1\:V.

All the transistors have the same output resistance

r_{ds}

of

6\:M\Omega.

The other parameters are listed below:

\mu_{n}=C_{ox}=60\: \mu A/V^{2}; \left(\frac{W}{L}\right)_{nMOS}=5

…

Two identical

\text{nMOS}

transistors

M_{1}

and

M_{2}

are connected as shown below. The circuit is used as an amplifier with the input connected between

\text{G and S}

terminals and the output taken between

D\: \text{and}\: S

terminals.

V_{bias}

and

V_{D}

are so adjusted that both transistors are in saturation. The …

In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is

2.5\: volts

. At the input, unit step voltage is applied, i.e.

v_{IN}\left ( t \right ) = u\left ( t \right )\:volts

. Also, at

t = 0

, the voltage across each of the capacitors is zero. The time

t

, in milliseconds, at which the output voltage

v_{OUT}

crosses …

In a

\text{p-n}

junction diode at equilibrium, which one of the following statements is NOT TRUE?

A

\text{p-n}

step junction diode with a contact potential of

0.65\:V

has a depletion width of

1\:\mu m

at equilibrium. The forward voltage (in volts, correct to two decimal places) at which this width reduces to

0.6\:\mu m

is __________.

There are two photolithography systems: one with light source of wavelength

\lambda _{1}=156\:nm

(System

1

) and another with light source of wavelength

\lambda _{2}=325\:nm

(System

2

). Both photolithography systems are otherwise identical. If the minimum feature sizes that can be realized using system

1

and system

2

are

L_{min1}

and …

The circuit shown in the figure is used to provide regulated voltage

(5 V)

across the

1\: k\Omega

resistor. Assume that the Zener diode has a constant reverse breakdown voltage for a current range, starting from a minimum required Zener current,

I_{Z min}=2\:mA

to its maximum allowable current. The input voltage

V_{I}

may vary by

5\%

from …

Red (R), Green(G) and Blue (B) Light Emitting Diodes (LEDs) were fabricated using

\text{p-n}

junctions of three different inorganic semiconductors having different band-gaps. The built-in voltages of red,green and blue diodes are

V_{R}

,

V_{G}

and

V_{B},

respectively. Assume donor and acceptor doping to be the same (

N_{A}

and

N_{D},

…

A solar cell of area

1.0\:cm^{2},

operating at

1.0

sun intensity, has a short circuit current of

20\: mA

, and an open circuit voltage of

0.65\: V

. Assuming room temperature operation and thermal equivalent voltage of

26\: mV

, the open circuit voltage (in volts, correct to two decimal places) at

0.2

sun intensity is _________.

In the circuit shown, the positive angular frequency

\omega

(in radians per second) at which the magnitude of the phase difference between the voltages

V_1

and

V_2

equals

\frac{\pi}{4}

radians, is _________

An

n^+-n

Silicon device is fabricated with uniform and non-degenerate donor doping concentrations of

N_{D1}=1\times 10^{18}cm^{-3}

and

N_{D2}=1\times 10^{15}cm^{-3}

corresponding to the

n^+

and

n

regions respectively. At the operational temperature

T

, assume complete impurity ionization.

kT/g=25mV

, and intrinsic carrier …

The dependence of drift velocity of electrons on electric field in a semiconductor is shown below. The semiconductor has a uniform electron concentration of

n=1 \times 10^{16} cm^{3}

and electronic charge

q=1.6 \times 10 ^{-19}C

. If a bias of

5 V

is applied across a

1 µm

region of this semiconductor, the resulting current density in this …

As shown , a uniformly doped Silicon bar of length

L=0.1\mu m

with a donor concentration

N_{D}=10^{16}cm^{-3}

is illuminated at

x=0

such that electron and hole pairs are generated at the rate of

G_{L}=G_{L0}(1-\frac{x}{L}), 0\leq x\leq L

, where

G_{L0}=10^{17}cm^{-3}s^{-1}

. Hole life time is

10^{-4} s

, electronic charge …

As shown, two Silicon (Si) abrupt

p-n

junction diodes are fabricated with uniform donor doping concentrations of

N_{D1}=10^{14} cm^{-3}

and

N_{D2}=10^{16}cm^{-3}

in the

n

-regions of the diodes, and uniform acceptor doping concentrations of

N_{A1}=10^{14} cm^{-3}

and

N_{A2}=10^{16} cm{-3}

in the

p

-regions of the …

An n-channel enhancement mode MOSFET is biased at

V_{GS}

>

V_{TH}

and

V_{DS}

>

(V_{GS}-V_{TH})

, where

V_{GS}

is the gate-to-source voltage,

V_{DS}

is the drain-to-source voltage and

V_{TH}

is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a