GATE EC Digital Circuits questions

​​​​​The sequence of states $\left(Q_{1} Q_{0}\right)$ of the given synchronous sequential circuit is - $\_\_\_\_\_\_\_$.

​​​​​A full scale sinusoidal signal is applied to a $10$ -bit $\mathrm{ADC}$. The fundamental signal component in the $\mathrm{ADC}$ output has a normalized power of $1 \mathrm{~W}$, and the total noise and distortion normalized power is $10 \mu \mathrm{W}$. The effective number of bits (rounded off to the nearest integer) of the $\mathrm{ADC}$ …

In the circuit shown below, the transistors $M_{1}$ and $M_{2}$ are biased in saturation. Their small signal transconductances are $g_{m 1}$ and $g_{m 2}$ respectively. Neglect body effect, channel length modulation and intrinsic device capacitances. Assuming that capacitor $C_{1}$ is a short circuit for $\mathrm{AC}$ analysis, the exact …

The signal-to-noise ratio $\mathrm{SNR}$ of an $\mathrm{ADC}$ with a full-scale sinusoidal input is given to be $61.96 \mathrm{~dB}$. The resolution of the $\mathrm{ADC}$ is_____________bits (rounded off to the nearest integer).

A sample and hold circuit is implemented using a resistive switch and a capacitor with a time constant of $1 \; \mu \mathrm{s}$. The time for the sampling switch to stay closed to charge a capacitor adequately to a full scale voltage of $1 \mathrm{~V}$ with $12$-bit accuracy is ___________ $\mu \mathrm{s}$ (rounded off to two decimal places).

In the circuit shown below, $\mathrm{P}$ and $\mathrm{Q}$ are the inputs. The logical function realized by the circuit shown below is

The synchronous sequential circuit shown below works at a clock frequency $1 \; \mathrm{GHz}$. The throughput, in $\text{Mbits/s,}$ and the latency, in $\text{ns,}$ respectively, are

For the circuit shown below, the propagation delay of each $\mathrm{NAND}$ gate is $1 \mathrm{~ns}$. The critical path delay, in $\text{ns,}$ is______________(rounded off to the nearest integer).

In a given sequential circuit, initial states are $Q_1=1$ and $Q_2=0$. For a clock frequency of $1 \; \mathrm{MHz}$, the frequency of signal $\mathrm{Q}_2$ in $\mathrm{kHz}$, is __________ (rounded off to the nearest integer).

Consider the $\text{2–bit}$ multiplexer $\text{(MUX)}$ shown in the figure. For $\text{OUTPUT}$ to be the $\text{XOR}$ of $\text{C}$ and $\text{D},$ the values for $A_{0}, A_{1}, A_{2},$ and $A_{3}$ are _______________.

Select the Boolean function(s) equivalent to $x+yz,$ where $x, y,$ and $z$ are Boolean variables, and $+$ denotes logical $\text{OR}$ operation.

Select the correct statement(s) regarding $\text{CMOS}$ implementation of $\text{NOT}$ gates.

For the circuit shown, the clock frequency is $f_{0}$ and the duty cycle is $25 \%.$ For the signal at the $\text{Q}$ output of the Flip-Flop, _______________.

Consider a Boolean gate $\text{(D)}$ where the output $Y$ is related to the inputs $A$ and $B$ as, $Y = A + \overline{B},$ where $+$ denotes logical $\text{OR}$ operation. The Boolean inputs $’0’$ and $’1’$ are also available separately. Using instances of only $\text{D}$ gates and inputs $’0’$ and $’1’,$ _______________ (select the …

​​​​​​​If $(1235)_{x}\:=\:(3033)_{y}$, where $x$ and $y$ indicate the bases of the corresponding numbers, then

​​​​​​Addressing of a $32K\:\times\:16$ memory is realized using a single decoder. The minimum number of $\text{AND}$ gates required for the decoder is

An $8$-bit unipolar (all analog output values are positive) digital-to-analog converter $\text{(DAC)}$ has a full-scale voltage range from $0\; V$ to $7.68\:V$. If the digital input code is $10010110$ (the leftmost bit is $\text{MSB}$), then the analog output voltage of the $\text{DAC}$ (rounded off to one decimal place) is ___________ $V$.

​​​​​​​The propagation delays of the $\text{XOR}$ gate, $\text{AND}$ gate and multiplexer $\text{(MUX)}$ in the circuit shown in the figure are $4\:ns$, $2\:ns$ and $1\:ns$, respectively. If all the inputs $\text{P, Q, R, S and T}$ are applied simultaneously and held constant, the maximum propagation delay of the circuit is

The content of the registers are $R_{1} = 25H, R_{2} = 30H$ and $R_{3} = 40H$. The following machine instructions are executed. $\text{PUSH } \{R_{1}\}$ $\text{PUSH } \{R_{2}\}$ $\text{PUSH } \{R_{3}\}$ $\text{POP } \{R_{1}\}$ $\text{POP } \{R_{2}\}$ $\text{POP } \{R_{3}\}$ After execution, the content of registers $R_{1},\:R_{2},\:R_{3}$ …

The propagation delay of the exclusive$-\text{OR}$ ($\text{XOR}$) gate in the circuit in the figure is $3\:ns$. The propagation delay of all the flip-flops is assumed to be zero. The clock ($\text{Clk}$) frequency provided to the circuit is $500\: \text{MHz}$. Starting from the initial value of the flip-flop outputs $Q_{2}Q_{1}Q_{0} = 1\;1\;1$ …