GATE EC Digital Circuits questions

The number of product terms in the minimized sum-of-product expression obtained through the following $\text{K}$-map is (where, " $d$ " denotes don't care states) $$\begin{array}{|c|c|c|c|} \hline 1 & 0 & 0 & 1 \\ \hline 0 & d & 0 & 0 \\ \hline 0 & 0 & d & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline \end{array}$$

A new Binary Coded Pentary (BCP) number system is proposed in which every digit of a base-$5$ number is represented by tis corresponding $3$-bit binary code. For example, the base-$5$ number $24$ will be represented by its BCP code $010100.$ In this numbering system, the BCP code $100010011001$ corresponds to the following number in base-$5$ …

An $\frac{\mathrm{I}}{\mathrm{O}}$ peripheral device shown in Figure $(b)$ below is to be interfaced to an $8085$ microprocessor. To select the $\frac{\mathrm{I}}{\mathrm{O}}$ device in the $\frac{\mathrm{I}}{\mathrm{O}}$ address range $\mathrm{D} 4 \mathrm{H}-\mathrm{D} 7 \mathrm{H}$, its chip-select $(\overline{C S})$ should be connected to …

For the circuit shown in figure below, two $4$-bit parallel-in serial-out shift registers loaded with the data shown are used to feed the data to a full adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, the outputs of the fulladder should be

Two $\text{D}$-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following $\mathrm{Q}_{1} \mathrm{Q}_{0}$ sequence $00 \longrightarrow 01 \longrightarrow 11 \longrightarrow 10 \longrightarrow 00 \longrightarrow \dots$ The inputs $D_{0}$ and $D_{1}$ respectively should be connected as

Following is the segment of a $8085$ assembly language program $\text{LXISP,EFFFH}$ $\text{CALL 3000 H}$ $3000 \mathrm{H}: \mathrm{LXIH}, 3 \mathrm{CF} 4 \mathrm{H}$ $\text{PUSH PSW}$ $\text{SPIH}$ $\text{POP PSW}$ $\text{RET}$ On completion of $\text{RET}$ execution, the contents of $\mathrm{SP}$ is

The point $\text{P}$ in the following figure is stuck-at-$1$. The output $f$ will be

Decimal $43$ in Hexadecimal and $\text{BCD}$ number system is respectively

The Boolean function $f$ implemented in the figure using two input multiplexers is

The Boolean expression for the truth table shown is …

The present output $Q_{n}$ of an edge triggered JK flip-flop is logic $0.$ If $\mathrm{J}=1$, then $\mathrm{Q}_{n+1}$

The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is $Q_{2} \; Q_{1} \; Q_{0}=011$, then its next state $\left(Q_{2} \; Q_{1} \; Q_{n}\right)$ will be

What memory address range is $\text{NOT}$ represented by chip $\# \; 1$ and chip $\# \; 2$ in the figure $\text{A}_{0}$ to $\text{A}_{15}$ in this figure are the address lines and $\text{CS}$ means Chip Select.

Statement for Linked Answer Questions 81 a and 81 b: Consider an $8085$ microprocessor system The following program starts at location $0100 \mathrm{H}$. $\begin{array}{l} \text{LXI SP, 00FF} \\ \text{LXI H, 0701} \\ \text{MVI A, 20H} \\ \text{SUB M} \end{array}$ The content of accumulator when the program counter reaches $0109 \mathrm{H}$ is

Statement for Linked Answer Questions 83a and 83b: Asymmetric three-level midtread quantizer is to be designed assuming equiprobable occurence of all quantization levels. If the probability density function is divided into three regions as shown in the figure, the value of a in the figure is

A master-slave flip-flop has the characteristic that

The range of signed decimal numbers that can be represented by $6$-bite $1$'s complement number is

A digital system is required to amplify a binary-encoded audio signal. The user should be able to control the gain of the amplifier from a minimum to a maximum in $100$ increments. The minimum number of bits required to encode, in straight binary, is

Choose the correct one from among the alternatives $\text{A, B, C, D}$ after matching an item from Group $1$ with the most appropriate item in Group $2.$ …

Figure given below shows the internal schematic of a $\text{TTL AND-OR}$ -Invert $\text{(AOI)}$ gate. For the inputs shown in the given figure, the output $\text{Y}$ is