GATE EC Analog Circuits questions

An analog voltage in the range $0$ to $8$ V is divided in $16$ equal intervals for conversion to $4$-bit digital output. The maximum quantization error (in V) is __________

In the circuit shown, the silicon BJT has $\beta = 50$. Assume $V_{BE}= 0.7 \: V$ and $V_{CE(sat)}= 0.2 \: V$. Which one of the following statements is correct?

Assuming that the Op-amp in the circuit shown is ideal, $V_{o}$ is given by

The circuit shown in the figure represents a

The circuit shown represents

Consider two BJTs biased at the same collector current with area $A_1=0.2 \mu m \times 0.2 \mu m$ and $A_2 = 300 \mu m \times 300 \mu m$. Assuming that all other device parameters are identical, $kT/q=26 \: mV$, the intrinsic carrier concentration is $1 \times 10^{10} cm^{-3}$, and $q=1.6 \times 10^{-19} \:C$, the difference between the …

Consider the common-collector amplifier in the figure (bias circuitry ensures that the transistor operates in forward active region, but has been omitted for simplicity). Let $I_C$ be the collector current, $V_{BE}$ be the base-emitter voltage and $V_T$ be the thermal voltage. Also, $g_m$ and $r_0$ are the small-signal transconductance and output …

A BJT in a common-base configuration is used to amplify a signal received by a $50 \Omega$ antenna. Assume $kT/q=25 \: mV$. The value of the collector bias current (in mA) required to match the input impedance of the amplifier to the impedance of the antenna is __________.

For the common collector amplifier shown in the figure, the BJT has high $\beta$, negligible $V_{CE(sat)}$, and $V_{BE}=0.7 \: V$. The maximum undistorted peak-to-peak output voltage $v_o$ (in Volts) is __________

In a forward biased $pn$ junction diode, the sequence of events that best describes the mechanism of current flow is

In the circuit shown below the $\text{op-amps}$ are ideal. Then $V_{\text{out}}$ in $\text{Volts}$ is

In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is $+5 V, X$ and $Y$ are digital signals with $0\: V$ as logic $0$ and $V_{cc}$ as logic $1,$ then the Boolean expression for $Z$ is

A voltage $1000 \sin\omega t\:\: \text{Volts}$ is applied across $YZ.$ Assuming ideal diodes, the voltage measured across $WX$ in $\text{Volts},$ is

The diodes and capacitors in the circuit shown are ideal. The voltage $v(t)$ across the diode $D1$ is

The input $x(t)$ and output $y(t)$ of a system are related as $y(t)=\underset{-\infty}{\int}x(\tau)\cos(3\tau)d\tau$. The system is

The feedback system shown below oscillates at $2\:rad/s$ when

Assuming both the voltage sources are in phase, the value of $R$ for which maximum power is transferred from circuit $A$ to circuit $B$ is

The voltage gain $A_v$ of the circuit shown below is

In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at every p-n junction is $10\:nm$. The relative permittivities of $Si$ and $SiO_2$, respectively, are $11.7$ and $3.9$, and $\varepsilon_0=8.9 \times 10^{-12} \: F/m$. The …

In the three dimensional view of a silicon n-channel MOS transistor shown below, $\delta=20\:nm$. The transistor is of width $1\: \mu m$. The depletion width formed at every p-n junction is $10\:nm$. The relative permittivities of $Si$ and $SiO_2$, respectively, are $11.7$ and $3.9$, and $\varepsilon_0=8.9 \times 10^{-12} \: F/m$. The …