GATE CS Computer Organization and Architecture questions
Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.
Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.
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The address space of CPU is
Which of the following is true?
Which of the following addressing modes permits relocation without any change whatsoever in the code?
A micro instruction is to be designed to specify: none or one of the three micro operations of one kind and none or upto six micro operations of another kind The minimum number of bits in the micro-instruction is:
The correct matching for the following pairs is:
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: …
A hard disk is connected to a MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires clock cycles for the processor. The hard disk has a transfer rate of Kbytes/sec and average block …
A micro program control unit is required to generate a total of control signals. Assume that during any micro instruction, at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be:
For the daisy chain scheme of connecting I/O devices, which of the following statements is true?
Relative mode of addressing is most relevant to writing:
A computer system has a word cache organized in block-set-associative manner with blocks per set, words per block. The number of bits in the SET and WORD fields of the main memory address format is:
The principle of locality justifies the use of:
In a vectored interrupt:
Which of the following statements is true?
State True or False with one line explanation Expanding opcode instruction formats are commonly employed in RISC. (Reduced Instruction Set Computers) machines.
The access times of the main memory and the Cache memory, in a computer system, are n sec and nsec, respectively. It is estimated that of the main memory request are for read the rest for write. The hit ratio for the read access only is and a write-through policy (where both main and cache memories are updated simultaneously) …
In an -bit computer instruction format, the size of address field is -bits. The computer uses expanding OP code technique and has two-address instructions and one-address instructions. The number of zero-address instructions it can support is ________
The total size of address space in a virtual memory system is limited by:
A block-set associative cache memory consists of blocks divided into four block sets. The main memory consists of blocks and each block contains eight bit words. How many bits are required for addressing the main memory? How many bits are needed to represent the TAG, SET and WORD fields?
State whether the following statements are TRUE or FALSE with reason: The flags are affected when conditional CALL or JUMP instructions are executed.