GATE CS 1998 Q2.10 — Machine Instructions and Addressing Modes

Match each addressing mode in $\textbf{List I}$ with a data element or an element of a data structure (in a high-level language) in $\textbf{List II}$: …

Consider a processor $\text{P}$ whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following sequences of instructions corresponds to the high-level language statement $\mathrm{Z}=\mathrm{X}+\mathrm{Y}$ ? Note: X, Y, and Z …

Consider a processor that has $16$ general purpose registers and it uses $2$-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has $2$ register operands and a $6$-bit immediate operand. Each Rtype instruction has …

A processor has $64$ general-purpose registers and $50$ distinct instruction types. An instruction is encoded in $32$-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction? $\text{ADD R1}$, $\#25$ / / $\text{R 1=R 1+25}$

An application executes $6.4 \times 10^{8}$ number of instructions in $6.3$ seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is __________. (rounded off to one decimal place) …

​​​​Which of the following is/are part of an Instruction Set Architecture of a processor?