GATE EC question library

The rank of the matrix $\begin{bmatrix} 1 & -1& 0& 0& 0& \\ 0& 0& 1& -1& 0& \\ 0& 1& -1& 0& 0& \\ -1& 0& 0& 0& 1& \\ 0& 0& 0& 1& -1& \end{bmatrix}$ is ________.

The general solution of the differential equation $\frac{d^2y}{dx^2}+2\frac{dy}{dx}-5y=0$ in terms of arbitrary constants $K_1$ and $K_2$ is

The smaller angle (in degrees) between the planes $x+y+z=1$ and $2x-y+2z=0$ is ________.

The residues of a function $$f(z)=\frac1{(z-4)(z+1)^3 }$$ are

In the circuit shown, V is a sinusoidal voltage source. The current $I$ is in phase with voltage V. The ratio$\frac{\text{amplitude of voltage across the capacitor}}{\text{amplitude of voltage across the resistor}}$ is ___________.

A connection is made consisting of resistance A in series with a parallel combination of resistances $B$ and $C$. Three resistors of value $10 Ω, 5 Ω, 2 Ω$ are provided. Consider all possible permutations of the given resistors into the positions $A, B, C$, and identify the configurations with maximum possible overall resistance, and also the ones …

An LTI system with unit sample response $h[n]=5\delta [n]-7\delta [n-1]+7\delta [n-3]-5\delta [n-4]$ is a

The input $x(t)$ and the output $y(t)$ of a continuous –time system are related as $$y(t)=\int_{t-T}^{t}x(u) du.$$ The system is

An n-channel enhancement mode MOSFET is biased at $V_{GS}$ >$V_{TH}$ and $V_{DS}$ > $(V_{GS}-V_{TH})$, where $V_{GS}$ is the gate-to-source voltage, $V_{DS}$ is the drain-to-source voltage and $V_{TH}$ is the threshold voltage. Considering channel length modulation effect to be significant, the MOSFET behaves as a

An $npn$ bipolar junction transistor (BJT) is operating in the active region. If the reverse bias across the base-collector junction is increased, then

Consider an $n$-channel MOSFET having width $W$, length $L$, electron mobility in the channel $\mu _{n}$ and oxide capacitance per unit area $C_{ox}$. If gate-to-source $V_{GS}=0.7$ V, drain-to-source voltage $V_{DS}=0.1 V$, $\mu _{n}C_{ox}=100 \mu A/V^{2}$, threshold voltage $V_{TH}=0.3V$ and $(W/L)=50$, then the transconductance …

The output $V_0$ of the diode circuit shown in the figure is connected to an averaging DC voltmeter. The reading on the DC voltmeter in Volts, neglecting the voltage drop across the diode, is _________________.

In the figure, $D1$ is a real silicon $pn$ junction diode with a drop of $0.7V$ under forward bias condition and $D2$ is a Zener diode breakdown voltage of $-6.8V$. The input $V_{in}(t)$ is a periodic square wave of period $T$, whose one period is shown in the figure. Assuming $10 \tau < < T$, where $\tau$ is the time constant of the …

Consider the circuit shown in the figure. Assume base-to-emitter voltage $V_{BE}=0.8 V$ and common-base current gain ($\alpha$) of the transistor is unity. The value of the collector-to-emitter voltage $V_{CE}$ (in volt) is ____________

For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is

Consider the circuit shown in the figure. The Boolean expression $F$ implemented by the circuit is

In a DRAM,

For the system shown in the figure, $Y(s)/X(s)$ = ___________

Consider the state space realization $\begin{bmatrix} \dot{x_1}(t)\\ \dot{x_2}(t) \end{bmatrix}=\begin{bmatrix} 0 &0 \\ 0&-9 \end{bmatrix}\begin{bmatrix} x_1(t)\\ x_2(t) \end{bmatrix}+\begin{bmatrix} 0\\ 45 \end{bmatrix} u(t)$ , with the initial condition $\begin{bmatrix} x_1(0)\\ x_2(0) \end{bmatrix}=\begin{bmatrix} 0\\ 0 \end{bmatrix}$ , where …

Which of the following statements is incorrect?