GATE EC question library

The following arrangement consists of an ideal transformer and an attenuator which attenuates by a factor of $0.8.$ An ac voltage $V_{WX1} = 100V$ is applied across $WX$ to get an open circuit voltage $V_{YZ1}$ across $YZ.$ Next, an ac voltage $V_{YZ2}= 100V$ is applied across $YZ$ to get an open circuit voltage $V_{WX2}$ across $WX.$ Then …

Two magnetically uncoupled inductive coils have $Q$ factors $q_{1}$ and $q_{2}$ at the chosen operating frequency. Their respective resistances are $R_{1}$ and $R_{2}.$ When connected in series, their effective $Q$ factor at the same operating frequency is

The impulse response of a continuous time system is given by $h(t) = \delta(t-1) + \delta(t-3).$ The value of the step response at $t = 2$ is

The small-signal resistance $(i.e., dV_{B}/dI_{D})$ in $k\Omega$ offered by the $n$-channel $MOSFET\: M$ shown in the figure below, at a bias point of $V_{B} = 2\: V$ is (device data for $M:$ device transconductance parameter $k_{N} = \mu_{n} C'_{ox} (W/L) = 40\: \mu A/V^{2},$threshold voltage $V_{TN} = 1\: V,$ and neglect body effect and …

The ac schematic of an $NMOS$ common-source stage is shown in the figure below, where part of the biasing circuits has been omitted for simplicity. For the $n$-channel $MOSFET\: M,$ the transconductance $g_{m} = 1\; mA/V,$ and body effect and channel length modulation effect are to be neglected. The lower cutoff frequency in $Hz$ of the circuit is …

A system is described by the differential equation $\dfrac{\mathrm{d}^{2} y}{\mathrm{d} x} + 5\dfrac{\mathrm{d}y }{\mathrm{d} x} + 6y(t) = x(t).$ Let $x(t)$ be a rectangular pulse given by $x(t) = \begin{cases} 1&0<t<2 \\ 0&\text{otherwise} \end{cases}$ Assuming that $y(0) = 0$ and $\dfrac{\mathrm{d}y }{\mathrm{d} x} = 0$ at $t=0,$ …

A system described by a linear, constant coefficient, ordinary, first order differential equation has an exact solution given by $y(t)$ for $t>0,$ when the forcing function is $x(t)$ and the initial condition is $y(0).$ If one wishes to modify the system so that the solution becomes $-2y(t)$ for $t>0,$ we need to

Consider two identically distributed zero-mean random variables $U$ and $V.$ Let the cumulative distribution functions of $U$ and $2V$ be $F(x)$ and $G(x)$ respectively. Then, for all values of $x$

The $\text{DFT}$ of a vector $\begin{bmatrix} a & b & c & d \end{bmatrix}$ is the vector $\begin{bmatrix} \alpha & \beta & \gamma & \delta \end{bmatrix}.$ consider the product …

The signal flow graph for a system is given below. The transfer function $\dfrac{Y(s)}{U(s)}$ for this system is

In the circuit shown below the $\text{op-amps}$ are ideal. Then $V_{\text{out}}$ in $\text{Volts}$ is

In the circuit shown below, $Q_{1}$ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If $V_{cc}$ is $+5 V, X$ and $Y$ are digital signals with $0\: V$ as logic $0$ and $V_{cc}$ as logic $1,$ then the Boolean expression for $Z$ is

A voltage $1000 \sin\omega t\:\: \text{Volts}$ is applied across $YZ.$ Assuming ideal diodes, the voltage measured across $WX$ in $\text{Volts},$ is

Three capacitors $C_{1}, C_{2}$ and $C_{3}$ whose values are $10\mu F, 5\mu F,$ and $2\mu F$ respectively, have breakdown voltages of $10V, 5V,$ and $2V$ respectively. For the interconnection shown below, the maximum safe voltage in Volts that can be applied across the combination, and the corresponding total charge in $\mu C$ stored in the …

There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $RAMs\: 1, 2, 3$ and $4$ respectively are mapped to addresses

In the circuit shown below, the silicon $npn$ transistor $Q$ has a very high value of $\beta.$ The required value of $R_{2}$ in $k\Omega$ to produce $I_{C} = 1\: mA$ is

Let $U$ and $V$ be two independent and identically distributed random variables such that $P(U=+1)=P(U=-1) = \dfrac{1}{2}.$ The entropy $H(U + V)$ in bits is

Bits $1$ and $0$ are transmitted with equal probability. At the receiver, the pdf of the respective received signals for both bits are as shown below. If the detection threshold is $1,$ the $BER$ will be

Bits $1$ and $0$ are transmitted with equal probability. At the receiver, the pdf of the respective received signals for both bits are as shown below. The optimum threshold to achieve minimum bit error rate $(BER)$ is

Consider the following figure The current $I_{S}$ in $\text{Amps}$ in the voltage source, and voltage $V_{S}$ in Volts across the current source respectively, are