GATE EC Sequential Circuits questions

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is $S_0$. If the input sequence is $10101101001101$, starting with the left-most bit, then the number of times 'Out' will be $1$ is ____________

Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor $R=10\Omega$ and the supply voltage is $5\:V$. The $D$ flip-flops $D_{1} \:, D_{2} \:, D_{3} \:, D_{4}$ and $D_{5}$ are initialized with logic values $0,1,0,1$ and $0$, respectively. The clocks has a $30\%$ duty cycle. The average power dissipated (in …

The state transition diagram for a finite state machine with states $A$, $B$ and $C$, and binary inputs $X$, $Y$ and $Z$, is shown in the figure. Which one of the following statements is correct?

For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________

For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a

A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

Five JK flip-flops are cascaded to form the circuit shown in Figure. Clock pulses at a frequency of $1\: MHz$ are applied as shown. The frequency $(\text{in}\:kHz)$ of the waveform at $Q3$ is ________.

The digital logic shown in the figure satisfies the given state diagram when $Q1$ is connected to input $A$ of the XOR gate. Suppose the XOR gate is replaced by an XNOR gate. Which one of the following options preserves the state diagram?

The outputs of the two flip-flops $Q1$, $Q2$ in the figure shown are initialized to $0,0$. The sequence generated at $Q1$ upon application of clock signal is

The circuit shown in the figure is a

Consider the given circuit. In the circuit, the race around

The state transition diagram for the logic circuit shown is

Refer to the NAND and NOR latches shown in the figure. The inputs $\left(P_{1}, P_{2}\right)$ for both the latches are first made $(0,1)$ and then, after a few seconds, made $(1,1)$. The corresponding stable outputs $\left(Q_{1}, Q_{2}\right)$ are

The following binary values were applied to the $\mathrm{X}$ and $\mathrm{Y}$ inputs of the NAND latch shown in the figure in the sequence indicated below: $$\mathrm{X}=0, \mathrm{Y}=1 ; \quad \mathrm{X}=0, \mathrm{Y}=0 ; \quad \mathrm{X}=1, \mathrm{Y}=1 \text{.}$$ The corresponding stable $\mathrm{P}, \mathrm{Q}$ outputs will be

For the circuit shown in figure below, two $4$-bit parallel-in serial-out shift registers loaded with the data shown are used to feed the data to a full adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, the outputs of the fulladder should be

Two $\text{D}$-flip-flops, as shown below, are to be connected as a synchronous counter that goes through the following $\mathrm{Q}_{1} \mathrm{Q}_{0}$ sequence $00 \longrightarrow 01 \longrightarrow 11 \longrightarrow 10 \longrightarrow 00 \longrightarrow \dots$ The inputs $D_{0}$ and $D_{1}$ respectively should be connected as

The present output $Q_{n}$ of an edge triggered JK flip-flop is logic $0.$ If $\mathrm{J}=1$, then $\mathrm{Q}_{n+1}$

The given figure shows a ripple counter using positive edge triggered flip-flops. If the present state of the counter is $Q_{2} \; Q_{1} \; Q_{0}=011$, then its next state $\left(Q_{2} \; Q_{1} \; Q_{n}\right)$ will be