GATE CS Memory Management and Virtual Memory questions

A system has a Translation Lookaside Buffer (TLB) that has a reach of $1$ MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size $4$ KB. The virtual address space is $64$ GB and physical address space is $1$ GB. If each TLB entry stores a $4$-bit process id, …

Consider contiguous allocation of physical memory to processes using variable partitioning scheme. Suppose there are $8$ holes in the memory of sizes $20 \mathrm{KB}, 4 \mathrm{~KB}$, $25 \mathrm{~KB}, 18 \mathrm{~KB}, 7 \mathrm{~KB}, 9 \mathrm{~KB}, 15 \mathrm{~KB}$, and $12$ KB. Assume that no two holes are adjacent. Two processes $\text{P1}$ of …

Consider a demand paging memory management system with $32$-bit logical address, $20$-bit physical address, and page size of $2048$ bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?

In optimal page replacement algorithm, information about all future page references is available to the operating system (OS). A modification of the optimal page replacement algorithm is as follows: The OS correctly predicts only up to next $4$ page references (including the current page) at the time of allocating a frame to a page. A process accesses the …

A computer system supports a logical address space of $2^{32}$ bytes. It uses two-level hierarchical paging with a page size of $4096$ bytes. A logical address is divided into a $b$-bit index to the outer page table, an offset within the page of the inner page table, and an offset within the desired page. Each entry of the inner page table uses eight …

​Consider a demand paging system with three frames, and the following page reference string: 1 2 3 4 5 4 1 6 4 5 1 3 2 . The contents of the frames are as follows initially and after each reference (from left to right): …

Consider a memory management system that uses a page size of $2 \mathrm{~KB}$. Assume that both the physical and virtual addresses start from $0$. Assume that the pages $0,1,2$, and $3$ are stored in the page frames $1,3,2$, and $0$, respectively. The physical address (in decimal format) corresponding to the virtual address $2500$ (in decimal …

​Which of the following tasks is/are the responsibility/responsibilities of the memory management unit $\text{(MMU)}$ in a system with paging-based memory management?

Consider a $32$-bit system with $4 \mathrm{~KB}$ page size and page table entries of size $4$ bytes each. Assume $1 \mathrm{~KB}=2^{10}$ bytes. The OS uses a $2$-level page table for memory management, with the page table containing an outer page directory and an inner page table. The $\text{OS}$ allocates a page for the outer page directory upon …

Consider a computer system with $57$-bit virtual addressing using multi-level tree-structured page tables with $\mathrm{L}$ levels for virtual to physical address translation. The page size is $4 \mathrm{~KB}(1 \mathrm{~KB}=1024 \mathrm{~B})$ and a page table entry at any of the levels occupies $8$ bytes. The value of $\mathrm{L}$ is …

Consider the following two-dimensional array $\text{D}$ in the $\text{C}$ programming language, which is stored in row-major order: int D[128][128]; Demand paging is used for allocating memory and each physical page frame holds $512$ elements of the array $\text{D}.$ The Least Recently Used $\text{(LRU)}$ page-replacement policy is used by the …

Which one of the following statements is $\text{FALSE}?$

Consider a demand paging system with four page frames (initially empty) and $\text{LRU}$ page replacement policy. For the following page reference string $$7, 2, 7, 3, 2, 5, 3, 4, 6, 7, 7, 1, 5, 6, 1$$ the page fault rate, defined as the ratio of number of page faults to the number of memory accesses $\textit{(rounded off to one decimal place)}$ is …

In the context of operating systems, which of the following statements is/are correct with respect to paging?

Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A process $P$ is currently using $2\text{GB}\;(1 \text{GB}=2^{30}$ bytes$)$ virtual memory which is mapped to …

Consider allocation of memory to a new process. Assume that none of the existing holes in the memory will exactly fit the process’s memory requirement. Hence, a new hole of smaller size will be created if allocation is made in any of the existing holes. Which one of the following statement is TRUE?

Consider a paging system that uses $1$-level page table residing in main memory and a $\textsf{TLB}$ for address translation. Each main memory access takes $100$ ns and $\textsf{TLB}$ lookup takes $20$ ns. Each page transfer to/from the disk takes $5000$ ns. Assume that the $\textsf{TLB}$ hit ratio is $95 \%$, page fault rate is $10 \%$. …

Assume that in a certain computer, the virtual addresses are $64$ bits long and the physical addresses are $48$ bits long. The memory is word addressible. The page size is $8$ kB and the word size is $4$ bytes. The Translation Look-aside Buffer (TLB) in the address translation path has $128$ valid entries. At most how many distinct virtual …

Consider a process executing on an operating system that uses demand paging. The average time for a memory access in the system is $M$ units if the corresponding memory page is available in memory, and $D$ units if the memory access causes a page fault. It has been experimentally measured that the average time taken for a memory access in the process is …

Recall that Belady's anomaly is that the page-fault rate may increase as the number of allocated frames increases. Now, consider the following statements: $S_1$: Random page replacement algorithm (where a page chosen at random is replaced) suffers from Belady's anomaly. $S_2$: LRU page replacement algorithm suffers from Belady's anomaly. Which of the …