GATE CS 2022 Q54 — Memory Management and Virtual Memory

A system has a Translation Lookaside Buffer (TLB) that has a reach of $1$ MB. TLB reach is defined as the total amount of physical memory that can be accessed through the TLB entries. The paging system uses pages of size $4$ KB. The virtual address space is $64$ GB and physical address space is $1$ GB. If each TLB entry stores a $4$-bit process id, …

Consider contiguous allocation of physical memory to processes using variable partitioning scheme. Suppose there are $8$ holes in the memory of sizes $20 \mathrm{KB}, 4 \mathrm{~KB}$, $25 \mathrm{~KB}, 18 \mathrm{~KB}, 7 \mathrm{~KB}, 9 \mathrm{~KB}, 15 \mathrm{~KB}$, and $12$ KB. Assume that no two holes are adjacent. Two processes $\text{P1}$ of …

Consider a demand paging memory management system with $32$-bit logical address, $20$-bit physical address, and page size of $2048$ bytes. Assuming that the memory is byte addressable, what is the maximum number of entries in the page table?

In optimal page replacement algorithm, information about all future page references is available to the operating system (OS). A modification of the optimal page replacement algorithm is as follows: The OS correctly predicts only up to next $4$ page references (including the current page) at the time of allocating a frame to a page. A process accesses the …

A computer system supports a logical address space of $2^{32}$ bytes. It uses two-level hierarchical paging with a page size of $4096$ bytes. A logical address is divided into a $b$-bit index to the outer page table, an offset within the page of the inner page table, and an offset within the desired page. Each entry of the inner page table uses eight …

​Consider a demand paging system with three frames, and the following page reference string: 1 2 3 4 5 4 1 6 4 5 1 3 2 . The contents of the frames are as follows initially and after each reference (from left to right): …