GATE CS Digital Logic questions

When two $8\text{-bit}$ numbers $A_{7}\cdots A_{0}$ and $B_{7}\cdots B_{0}$ in $2$'s complement representation (with $A_{0}$ and $B_{0}$ as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are $S_{7}\cdots S_{0}$ and the carry bits are $C_{7}\cdots C_{0}$. An overflow is said to have occurred if

The n-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i = n-f$. The range of decimal values for $X$ in this representation is

The next state table of a $2-$bit saturating up-counter is given below. $\begin{array}{cc|cc} Q_1 & Q_0 & Q_1^+ & Q_0^+ \\ \hline 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 \\ 1 & 1 & 1 & 1 \end{array}$ The counter is built as a synchronous sequential circuit using $T$ flip-flops. The …

If $w, x, y, z$ are Boolean variables, then which one of the following is INCORRECT?

Given the following binary number in $32$-bit (single precision) $\text{IEEE-754}$ format : $\large 00111110011011010000000000000000$ The decimal value closest to this floating-point number is :

Given $f(w, x, y, z) = \Sigma_m(0,1, 2, 3, 7, 8, 10) + \Sigma_d(5, 6, 11, 15)$; where $d$ represents the 'don't-care' condition in Karnaugh maps. Which of the following is a minimum product-of-sums (POS) form of $f(w, x, y, z)$?

The representation of the value of a $16\text{-bit}$ unsigned integer $X$ in hexadecimal number system is $\textsf{BCA9}$. The representation of the value of $X$ in octal number system is

Consider the two cascade $2$ to $1$ multiplexers as shown in the figure . The minimal sum of products form of the output $X$ is

Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

The $16\text{-bit}\;2's$ complement representation of an integer is $1111 \quad 1111 \quad 1111 \quad 0101;$ its decimal representation is ____________

Consider the Boolean operator # with the following properties : $x \# 0 = x, x \# 1=\overline{x}, x \# x = 0$ and $x \# \overline{x} = 1.$ Then $x\#y$ is equivalent to

Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________

Let $X$ be the number of distinct $16$-bit integers in $2's$ complement representation. Let $Y$ be the number of distinct $16$-bit integers in sign magnitude representation Then $X - Y$ is______.

Let, $x_{1} ⊕ x_{2} ⊕ x_{3} ⊕ x_{4}= 0$ where $x_{1}, x_{2}, x_{3}, x_{4}$ are Boolean variables, and $⊕$ is the XOR operator. Which one of the following must always be TRUE?

Consider the operations $\textit{f (X, Y, Z) = X'YZ + XY' + Y'Z'}$ and $\textit{g (X, Y, Z) = X'YZ + X'YZ' + XY}$ Which one of the following is correct?

A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ flip-flop, while the $Q$ output of the $JK$ flip-flop is connected to the input of the $D$ flip-flop. Initially, the output of the $D$ …

Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is $1.2$ microseconds. A $4$-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time …

The number of min-terms after minimizing the following Boolean expression is _______. $[D'+AB'+A'C+AC'D+A'C'D]'$