GATE CS 2001 Q2.8 — Combinational Circuits

To determine the correct waveform for $Y$, we trace the state transitions of the two D flip-flops, $FF_0$ and $FF_1$, at each positive edge of the clock $C$.

From the circuit diagram, the inputs to the flip-flops are:

• $D_0 = X$
• $D_1 = Q_0$

The output is given by the AND gate: $Y = Q_0 \cdot \overline{Q_1}$.

Given that the setup time is $20\text{ ns}$ and the clock period is $T \ge 40\text{ ns}$, the inputs satisfy the setup and hold time requirements. Let's analyze the state transitions at each positive clock edge:

1. Initial State: $Q_0 = 0$, $Q_1 = 0$. Thus, $Y = 0 \cdot \overline{0} = 0$.
2. First Positive Edge:
   • $X$ has been high ($1$) for more than $20\text{ ns}$ before this edge, so $Q_0$ becomes $1$.
   • $Q_1$ takes the previous value of $Q_0$, which was $0$.
   • Thus, $Q_0 = 1, Q_1 = 0 \implies Y = 1 \cdot \overline{0} = 1$.
3. Second Positive Edge:
   • $X$ has been low ($0$) for more than $20\text{ ns}$ before this edge, so $Q_0$ becomes $0$.
   • $Q_1$ takes the previous value of $Q_0$, which was $1$.
   • Thus, $Q_0 = 0, Q_1 = 1 \implies Y = 0 \cdot \overline{1} = 0$.
4. Third Positive Edge:
   • $X$ remains $0$, so $Q_0$ becomes $0$.
   • $Q_1$ takes the previous value of $Q_0$, which was $0$.
   • Thus, $Q_0 = 0, Q_1 = 0 \implies Y = 0 \cdot \overline{0} = 0$.

Therefore, $Y$ is high ($1$) only during the interval between the first and second positive clock edges, which corresponds to the waveform shown in Option A.