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GATE CS 2010 Q7 — Combinational Circuits

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The main memory unit with a capacity of 44 megabytes\text{megabytes} is built using 1M×1-bit1\text{M} \times \text{1-bit} DRAM chips. Each DRAM chip has 1K1\text{K} rows of cells with 1K1\text{K} cells in each row. The time taken for a single refresh operation is 100  nanoseconds100\; \text{nanoseconds}. The time required to perform one refresh operation on all the cells in the memory unit is

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Answer: B

In a DRAM, the refresh operation is performed on a row-by-row basis. When a row is selected for refreshing, all the cells in that row across all the chips in the memory unit are refreshed in parallel.

Let's break down the given parameters:

  • Each DRAM chip has 1K1\text{K} rows of cells (where 1K=2101\text{K} = 2^{10} rows).
  • The time taken to refresh a single row is 100 ns100\text{ ns}.

Since all chips are refreshed in parallel, the total number of refresh cycles required to refresh the entire memory unit is equal to the number of rows in a single chip:

Total Refresh Time=Number of rows×Time for a single refresh operation\text{Total Refresh Time} = \text{Number of rows} \times \text{Time for a single refresh operation} Total Refresh Time=1K×100 ns=100×210 nanoseconds\text{Total Refresh Time} = 1\text{K} \times 100\text{ ns} = 100 \times 2^{10}\text{ nanoseconds}

Therefore, the correct option is B.

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