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GATE EC question library

Practise GATE EC Electronics and Communication previous year questions free. Browse by subject, syllabus topic, year and question type, with answers and available solutions.

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Official PYQ2016Engineering MathematicsDifferential EquationsNAT · 2 marks
The ordinary differential equation dxdt=−3x+2, with x(0)=1\frac{dx}{dt}=-3x+2, \text{ with }x(0) = 1 is to be solved using the forward Euler method. The largest time step that can be used to solve the equation without making the numerical solution unstable is _________
Official PYQ2016Engineering MathematicsVector AnalysisNAT · 2 marks
Suppose CC is the closed curve defined as the circle x2+y2=1x^{2}+y^{2}=1 with CC oreinted anti-clockwise. The value of ∮\oint ( xy2xy^{2} dxdx + x2yx^{2}y dydy )over the curve CC equals _________
Official PYQ2016Engineering MathematicsProbability and StatisticsNAT · 2 marks
Two random variables XX and YY are distributed according to fX,Y(x,y)={(x+y),0≤x≤1,0≤y≤10,otherwise.f_{X,Y}(x,y)=\begin{cases} (x+y),& 0\leq x\leq 1,&0\leq y\leq 1\\ 0, & \text{otherwise.} \end{cases} The probability P(X+Y≤1)P(X+Y\leq 1) is ________
Official PYQ2016Engineering MathematicsLinear AlgebraNAT · 2 marks
The matrix A=[a03725130024000b]A=\begin{bmatrix} a & 0 &3 &7 \\ 2& 5&1 &3 \\ 0& 0& 2 &4 \\ 0&0 & 0 &b \end{bmatrix} has det(A)=100\text{det}(A) = 100 and trace(A)=14\text{trace}(A) = 14. The value of ∣a−b∣\mid a-b \mid is ________
Official PYQ2016Electronic DevicesMCQ · 2 marks
In the given circuit, each resistor has a value equal to 1Ω1\Omega. What is the equivalent resistance across the terminals aa and bb?
Official PYQ2016Electronic DevicesNAT · 2 marks
In the circuit shown in the figure, the magnitude of the current (in amperes) through R2R_{2} is ____
Official PYQ2016Networks, Signals and SystemsDiscrete-time SignalsNAT · 2 marks
A continuous-time filter with transfer function H(s)=2s+6s2+6s+8H\left ( s \right )= \frac{2s+6}{s^{2}+6s+8} is converted to a discrete-time filter with transfer function G(z)=2z2−0.5032 zz2−0.5032 z+kG\left ( z\right )= \frac{2z^{2}-0.5032 \: z}{z^{2}-0.5032 \: z+k} so that the impulse response of the continuous-time filter, sampled at 22 HzHz, is identical at the sampling instants to the …
Official PYQ2016Networks, Signals and SystemsDiscrete-time SignalsNAT · 2 marks
The Discrete Fourier Transform (DFT) of the 44-point sequence x[n]={x[0],x[1],x[2],x[3]}={3,2,3,4}x\left [ n \right ]=\left \{ x\left [ 0 \right ],x\left [ 1 \right ], x\left [ 2 \right ], x\left [ 3 \right ] \right \}= \left \{ 3,2,3,4 \right \} is …
Official PYQ2016Networks, Signals and SystemsCircuit AnalysisNAT · 2 marks
The switch SS in the circuit shown has been closed for a long time. It is opened at t=0t = 0 and remains open after that. Assume that the diode has zero reverse current and zero forward voltage drop. The steady state magnitude of the capacitor voltage VcV_{c} (in volts) is ______
Official PYQ2016Electronic DevicesMCQ · 2 marks
A voltage VGV_{G} is applied across a MOSMOS capacitor with metal gate and pp-type silicon substrate at T=300T=300 KK. The inversion carrier density (in number of carriers per unit area) for VG=0.8V_{G}= 0.8 VV is 2×1011cm−2.2\times 10^{11} cm^{-2}. For VG=1.3V_{G}= 1.3 VV, the inversion carrier density is 4×1011cm−2.4\times10^{11} cm^{-2}. What is the value of …
Official PYQ2016Electronic DevicesMCQ · 2 marks
Consider avalanche breakdown in a silicon p+np^{+}n junction. The nn-region is uniformly doped with a donor density ND.N_{D}. Assume that breakdown occurs when the magnitude of the electric field at any point in the device becomes equal to the critical field Ecrit.E_{crit}. Assume EcritE_{crit} to be independent of NDN_{D}. If the built-in voltage of the …
Official PYQ2016Electronic DevicesNAT · 2 marks
Consider a region of silicon devoid of electrons and holes, with an ionized donor density of Nd+=1017cm−3.N_{d}^{+}=10^{17} cm^{-3}. The electric field at x=0x = 0 is 0 V/cm0\: V/cm and the electric field at x=Lx=L is 5050 kV/cmkV/cm in the positive xx direction, Assume that the electric field is zero in the yy and zz directions at all points. Given …
Official PYQ2016Analog CircuitsBJT and MOSFET AmplifiersNAT · 2 marks
Consider a long-channel NMOSNMOS transistor with source and body connected together. Assume that the electron mobility is independent of VGSV_{GS} and VDS.V_{DS}. Given, gm=0.5μA/V for VDS=50 mV and  VGS=2 Vg_{m}=0.5\mu A/V \text{ for } V_{DS}=50\:mV \text{ and } \: V_{GS}= 2 \: V, gd=8μA/V for VGS=2 V and VDS=0 Vg_{d}=8\mu A/V \text{ for } V_{GS}=2\:V \text{ and }V_{DS}=0 \:V, where …
Official PYQ2016Electronic DevicesNAT · 2 marks
The figure shows a half-wave rectifier with a 475 μF475 \: \mu F filter capacitor. The load draws a constant current Io=1 AI_{o}= 1 \: A from the rectifier. The figure also shows the input voltage ViV_{i}, the output voltage VCV_{C} and the peak-to-peak voltage ripple uu on VCV_{C}. The input voltage ViV_{i} is a triangle-wave with an amplitude of …
Official PYQ2016Electronic DevicesNAT · 2 marks
In the opamp circuit shown, the Zener diodes Z1Z1 and Z2Z2 clamp the output voltage V0V_{0} to +5V+5V or −5V-5 V. The switch SS is initially closed and is opened at time t=0t=0. The time t=t1t=t_{1} (in seconds) at which V0V_{0} changes state is ________
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 2 marks
An opamp has a finite open loop voltage gain of 100100. Its input offset voltage Vios(=+5mV)V_{ios}(=+5mV) is modeled as shown in the circuit below. The amplifier is ideal in all other respects. VinputV_{\text{input}} is 25 mV25 \: mV. The output voltage (in millivolts) is _________
Official PYQ2016Digital CircuitsSemiconductor MemoriesMCQ · 2 marks
An 88 Kbyte ROM with an active low Chip Select input (CS‾)\left (\overline{CS}\right ) is to be used in an 80858085 microprocessor based system. The ROM should occupy the address range 1000H1000H to 2FFFH2FFFH. The address lines are designated as A15A_{15} to A0A_{0}, where A15A_{15} is the most significant address bit. Which one of the following logic …
Official PYQ2016Digital CircuitsData ConvertersMCQ · 2 marks
In an NN bit flash ADC, the analog voltage is fed simultaneously to 2N−12^{N}-1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source VinV_{in} (whose output is being converted to digital format) has a source resistance of 75 Ω75 \: \Omega as shown in the circuit …
Official PYQ2016Digital CircuitsSequential CircuitsMCQ · 2 marks
The state transition diagram for a finite state machine with states AA, BB and CC, and binary inputs XX, YY and ZZ, is shown in the figure. Which one of the following statements is correct?
Official PYQ2016Analog CircuitsOp-amp CircuitsNAT · 2 marks
In the feedback system shown below G(s)=1(s2+2s)G\left ( s \right )=\frac{1}{\left ( s^{2}+2s \right )}. The step response of the closed-loop system should have minimum settling time and have no overshoot. The required value of gain kk to achieve this is __________