GATE EC Digital Circuits questions

An N-type semiconductor having uniform doping is biased as shown in the figure. If $E_C$ is the lowest energy level of the conduction band, $E_V$ is the highest energy level of the valance band and $E_F$ is the Fermi level, which one of the following represents the energy band diagram for the biased N-type semiconductor?

An $8$- to $1$ multiplexer is used to implement a logical function $Y$ as shown in the figure. The output $Y$ is given by

An $8085$ microprocessor executes $“STA 1234H”$ with starting address location $1FFEH$ (STA copies the contents of the Accumulator to the $16$- bit address location). While the instruction is fetched and executed, the sequence of values written at the address pins $A_{15} – A_8$ is

For $8085$ microprocessor, the following program is executed. $\begin{array}{ll} & MVI\: A, 05H; \\ & MVI\: B, 05H; \\ PTR: & ADD \:B; \\ & DCR \:B; \\ & JNZ\: PTR; \\ & ADI\: 03H; \\ & HLT; \end{array}$ At the end of program, accumulator contains

Two magnetically uncoupled inductive coils have $Q$ factors $q_{1}$ and $q_{2}$ at the chosen operating frequency. Their respective resistances are $R_{1}$ and $R_{2}.$ When connected in series, their effective $Q$ factor at the same operating frequency is

There are four chips each of $1024\:\text{bytes}$ connected to a $16\:\text{bit}$ address bus as shown in the figure below. $RAMs\: 1, 2, 3$ and $4$ respectively are mapped to addresses

Consider the given circuit. In the circuit, the race around

The output $Y$ of a $2-\text{bit}$ comparator is logic $1$ whenever the $2-\text{bit}$ input $A$ is greater than the $2-\text{bit}$ input $B$. The number of combinations for which the output is logic $1$, is

In the circuit shown

In the sum of products function $f(X,Y,Z)=\sum(2,3,4,5)$, the prime implicants are

The state transition diagram for the logic circuit shown is

The logic function implemented by the circuit below is (ground implies a logic $\text{“0”})$

The output $\mathrm{Y}$ in the circuit below is always $\text{“1"}$ when

Match the logic gates in Column A with their equivalents in Column B.

For the output $\text{F}$ to be $1$ in the logic circuit shown, the input combination should be

The Boolean function realized by the logic circuit shown is

What are the minimum number of $2$-to-$1$ multiplexers required to generate a $2$-input $\text{AND}$ gate and a $2$-input $\text{Ex-OR}$ gate?

Refer to the NAND and NOR latches shown in the figure. The inputs $\left(P_{1}, P_{2}\right)$ for both the latches are first made $(0,1)$ and then, after a few seconds, made $(1,1)$. The corresponding stable outputs $\left(Q_{1}, Q_{2}\right)$ are

$\mathrm{X}=01110$ and $\mathrm{Y}=11001$ are two $5$-bit binary numbers represented in two's complement format. The sum of $\mathrm{X}$ and $\mathrm{Y}$ represented in two's complement format using $6$ bits is

The following binary values were applied to the $\mathrm{X}$ and $\mathrm{Y}$ inputs of the NAND latch shown in the figure in the sequence indicated below: $$\mathrm{X}=0, \mathrm{Y}=1 ; \quad \mathrm{X}=0, \mathrm{Y}=0 ; \quad \mathrm{X}=1, \mathrm{Y}=1 \text{.}$$ The corresponding stable $\mathrm{P}, \mathrm{Q}$ outputs will be