GATE EC 2019 Set 1 Q15 — Semiconductor Memories

In a DRAM,

An $8$ Kbyte ROM with an active low Chip Select input $\left (\overline{CS}\right )$ is to be used in an $8085$ microprocessor based system. The ROM should occupy the address range $1000H$ to $2FFFH$. The address lines are designated as $A_{15}$ to $A_{0}$, where $A_{15}$ is the most significant address bit. Which one of the following logic …

If WL is the Word Line and BL the Bit Line, an SRAM cell is shown in

In the circuit shown in the figure $\mathrm{A}$ is a parallel-in, parallel-out $4$ bit register, which loads at the rising edge of the clock $C$. The input lines are connected to a $4$ bit bus, $W.$ Its output acts as the input to a $16 \times 4$ ROM whose output is floating when the enable input $E$ is $0.$ A partial table of the contents of …

Each cell of a Static Random Access Memory contains

A memory system of size $26 \mathrm{~K}$ bytes is required to be designed using memory chips which have $12$ address lines and $4$ data lines each. The number of such chips required to design the memory system is