GATE EC 2003 Set 1 Q56 — Combinatorial Circuits

The DTL, TTL, ECL and CMOS families of digital $\mathrm{IC}_{\mathrm{s}}$ are compared in the following $4$ columns

$$\begin{array}{lllll} & \textbf{(P)} & \textbf{(Q)} & \textbf{(R)} & \textbf{(S)} \\ \text{Fanout is minimum} & \text{DTL} & \text{DTL} & \text{TTL} & \text{CMOS} \\ \text{Power consumption is minimum} & \text{TTL} & \text{CMOS} & \text{ECL} & \text{DTL} \\ \text{Propagation delay is minimum} & \text{CMOS} & \text{ECL} & \text{TTL} & \text{TTL} \end{array}$$

The correct column is