GATE CS Operating System questions

Consider the following statements with respect to user-level threads and kernel-supported threads context switch is faster with kernel-supported threads for user-level threads, a system call can block the entire process Kernel supported threads can be scheduled independently User level threads are transparent to the kernel Which of the above statements are …

A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most significant bits of the virtual address are used as index …

Suppose we want to synchronize two concurrent processes $P$ and $Q$ using binary semaphores $S$ and $T$. The code for the processes $P$ and $Q$ is shown below. …

Suppose we want to synchronize two concurrent processes $P$ and $Q$ using binary semaphores $S$ and $T$. The code for the processes $P$ and $Q$ is shown below. Process P: Process Q: while(1){ W: print '0'; print '0'; X: } while(1){ Y: print '1'; print '1'; Z: } Synchronization statements can be inserted only at points $W, X, Y,$ and $Z$ Which …

A uni-processor computer system only has two processes, both of which alternate $10$ $\text{ms}$ CPU bursts with $90$ $\text{ms}$ I/O bursts. Both the processes were created at nearly the same time. The I/O of both processes can proceed in parallel. Which of the following scheduling strategies will result in the least CPU utilization (over a long …

In a system with $\text{32 bit}$ virtual addresses and $\text{1 KB}$ page size, use of one-level page tables for virtual to physical address translation is not practical because of

Using a larger block size in a fixed block size file system leads to

A processor uses $2-level$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, the $10$ most significant bits of the virtual address are used as index into …

In the index allocation scheme of blocks to a file, the maximum possible size of the file depends on

Which combination of the following features will suffice to characterize an OS as a multi-programmed OS? More than one program may be loaded into main memory at the same time for execution If a program waits for certain events such as I/O, another program is immediately scheduled for execution If the execution of a program terminates, another program is …

The optimal page replacement algorithm will select the page that

Which of the following scheduling algorithms is non-preemptive?

Consider a disk with the $100$ tracks numbered from $0$ to $99$ rotating at $3000$ rpm. The number of sectors per track is $100$ and the time to move the head between two successive tracks is $0.2$ millisecond.

Consider a disk with the following specifications: 20 surfaces, 1000 tracks/surface, 16 sectors/track, data density 1 KB/sector, rotation speed 3000 rpm. The operating system initiates the transfer between the disk and the memory sector-wise. Once the head has been placed on the right track, the disk reads a sector in a single scan. It reads bits from the …

Consider Peterson's algorithm for mutual exclusion between two concurrent processes i and j. The program executed by process is shown below. repeat flag[i] = true; turn = j; while (P) do no-op; Enter critical section, perform actions, then exit critical section Flag[i] = false; Perform other non-critical section actions. Until false; For the program to …

Consider a machine with $64$ MB physical memory and a $32$-bit virtual address space. If the page size s $4$ KB, what is the approximate size of the page table?

Which of the following does not interrupt a running process?

Which of the following requires a device driver?

Consider a virtual memory system with FIFO page replacement policy. For an arbitrary page access pattern, increasing the number of page frames in main memory will

Where does the swap space reside?