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Official PYQ · 2003

GATE CS 2003 Q79 — Memory Management and Virtual Memory

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A processor uses 2-level\text{2-level} page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 3232 bits wide. The memory is byte addressable. For virtual to physical address translation, the 1010 most significant bits of the virtual address are used as index into the first level page table while the next 1010 bits are used as index into the second level page table. The 1212 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 44 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%\text{96\%}. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%\text{90\%}. Main memory access time is 1010 ns, cache access time is 11 ns, and TLB access time is also 11 ns.

Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x000000000x00000000, two contiguous data pages starting at virtual address 0x004000000x00400000, and a stack page starting at virtual address 0xFFFFF0000xFFFFF000. The amount of memory required for storing the page tables of this process is

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Answer: C

To find the total memory required for the page tables, we first determine the size of each page table level and identify how many tables of each level are needed.

1. Size of a Page Table:

  • The first-level page table is indexed by the 10 most significant bits (MSB), meaning it contains 210=10242^{10} = 1024 entries. Since each entry is 44 bytes, its size is 1024×4 bytes=4 KB1024 \times 4\text{ bytes} = 4\text{ KB}.
  • Each second-level page table is also indexed by 10 bits, containing 210=10242^{10} = 1024 entries. Its size is similarly 1024×4 bytes=4 KB1024 \times 4\text{ bytes} = 4\text{ KB}.

2. Number of Second-Level Page Tables Required:

We analyze the 10 MSBs of the virtual addresses for the given pages to see which entries of the first-level table are active:

  • Code pages: Starting at 0x000000000x00000000 and 0x000010000x00001000.
    The 10 MSBs for these addresses are 00000000002=00000000000_2 = 0. Both pages share the first-level entry at index 00, requiring 1 second-level page table.
  • Data pages: Starting at 0x004000000x00400000 and 0x004010000x00401000.
    The 10 MSBs for these addresses are 00000000012=10000000001_2 = 1. Both pages share the first-level entry at index 11, requiring 1 second-level page table.
  • Stack page: Starting at 0xFFFFF0000xFFFFF000.
    The 10 MSBs for this address are 11111111112=10231111111111_2 = 1023. This requires the first-level entry at index 10231023, requiring 1 second-level page table.

3. Total Memory Calculation:

  • We need 11 first-level page table and 33 second-level page tables.
  • Total page tables = 1+3=41 + 3 = 4.
  • Total memory required = 4×4 KB=16 KB4 \times 4\text{ KB} = 16\text{ KB}.

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