A processor uses page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both bits wide. The memory is byte addressable. For virtual to physical address translation, the most significant bits of the virtual address are used as index into the first level page table while the next bits are used as index into the second level page table. The least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of . The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of . Main memory access time is ns, cache access time is ns, and TLB access time is also ns.
Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address , two contiguous data pages starting at virtual address , and a stack page starting at virtual address . The amount of memory required for storing the page tables of this process is
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Answer: C
To find the total memory required for the page tables, we first determine the size of each page table level and identify how many tables of each level are needed.
1. Size of a Page Table:
- The first-level page table is indexed by the 10 most significant bits (MSB), meaning it contains entries. Since each entry is bytes, its size is .
- Each second-level page table is also indexed by 10 bits, containing entries. Its size is similarly .
2. Number of Second-Level Page Tables Required:
We analyze the 10 MSBs of the virtual addresses for the given pages to see which entries of the first-level table are active:
- Code pages: Starting at and .
The 10 MSBs for these addresses are . Both pages share the first-level entry at index , requiring 1 second-level page table. - Data pages: Starting at and .
The 10 MSBs for these addresses are . Both pages share the first-level entry at index , requiring 1 second-level page table. - Stack page: Starting at .
The 10 MSBs for this address are . This requires the first-level entry at index , requiring 1 second-level page table.
3. Total Memory Calculation:
- We need first-level page table and second-level page tables.
- Total page tables = .
- Total memory required = .
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