GATE EC question library

In the circuit shown, switch SW is closed at $t=0$. Assuming zero initial conditions, the value of $v_c(t)$ (in Volts) at $t=1$ sec is _________.

In the given circuit, the maximum power (in Watts) that can be transferred to the load $R_L$ is ________.

The built-in potential of an abrupt p-n junction is $0.75$ V. If its junction capacitance $(C_J)$ at a reverse bias $(V_R)$ of $1.25 \: V$ is $5$ pF, the value of $C_J$ (in pF) when $V_R = 7.25 \: V$ is ________.

A MOSFET in saturation has a drain current of $1$ mA for $V_{DS} =0.5 \: V$. If the channel length modulation coefficient is $0.05 \: V^{-1}$, the output resistance (in $k \Omega$) of the MOSFET is ___________.

For a silicon diode with long P and N regions, the accepter and donor impurity concentrations are $1 \times 10^{17} \:cm^{-3}$ and $1 \times 10^{15} \: cm^{-3}$, respectively. The lifetimes of electrons in P region and holes in N region are both $100 \: \mu s$. The electron and hole diffusion coefficients are $49 \: cm^2/s$ and $36 \: cm^2/s$, …

The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ converted into the canonical product of sum (POS) form is

All the logic gates shown in the figure have a propagation delay of $20$ ns. Let $A=C=0$ and $B=1$ until time $t=0$. At $t=0$, all the inputs flip (i.e., $A=C=1$ and $B=0$) and remain in that state. For $t>0$, output $Z=1$ for a duration (in ns) of ________.

A $3$-input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M(\overline{M(a,b,c)}, M(a,b,\overline{c}),c)$?

For the NMOSFET in the circuit shown, the threshold voltage is $V_{th}$, where $V_{th}>0$. The source voltage $V_{SS}$ is varied from $0$ to $V_{DD}$. Neglecting the channel length modulation, the drain current $I_D$ as a function of $V_{SS}$ is represented by

In the circuit shown, assume that the opamp is ideal. The bridge output voltage $V_0$ (in mV) for $\delta=0.05$ is __________

The circuit shown in the figure has an ideal opamp. The oscillation frequency and the condition to sustain the oscillations, respectively, are

In the circuit shown, $I_1=80$ mA and $I_2=4$ mA. Transistors $T_1$ and $T_2$ are identical. Assume that the thermal voltage $V_T$ is $26$ mV at $27^{\circ}C$. At $50^{\circ}C$, the value of the voltage $V_{12}=V_1 - V_2$ (in mV) is _______.

Two sequences $\begin{bmatrix}a, & b, & c \end{bmatrix}$ and $\begin{bmatrix}A, & B, & C \end{bmatrix}$ are related as, …

For the discrete-time system shown in the figure, the poles of the system transfer function are located at

The pole-zero diagram of a casual and stable discrete-time system is shown in the figure. The zero at the origin has multiplicity $4$. The impulse response of the system is $h[n]$. If $h[0]=1$, we can conclude

The open-loop transfer function of a plant in a unity feedback configuration is given as $G(s) = \frac{K(s+4)}{(s+8)(s^2-9)}$. The value of the gain $K(>0)$ for which $-1+j2$ lies on the root locus is _________.

A lead compensator network includes a parallel combination of $R$ and $C$ in the feed-forward path. If the transfer function of the compensator is $G_c(s)=\frac{s+2}{s+4}$, the value of $RC$ is ___________.

A plant transfer function is given as $G(s)= \bigg( K_p+ \frac{K_1}{s} \bigg) \frac{1}{s(s+2)}$. When the plant operates in a unity feedback configuration, the condition for the stability of the closed loop system is

The input $X$ to the Binary Symmetric Channel (BSC) shown in the figure is $’1’$ with probability $0.8$. The cross-over probability is $1/7$. If the received bit $Y=0$, the conditional probability that $’1’$ was transmitted is ____________

The transmitted signal in a GSM system is of $200$ kHz bandwidth and $8$ users share a common bandwidth using TDMA. If at a given time $12$ users are talking in a cell, the total bandwidth of the signal received by the base station of the cell will be at least (in kHz) ___________.