GATE EC Sequential Circuits questions

A master-slave flip-flop has the characteristic that

Choose the correct one from among the alternatives $\text{A, B, C, D}$ after matching an item from Group $1$ with the most appropriate item in Group $2.$ …

In the modulo-$6$ ripple counter shown in the given figure, the output of the $2$-input gate is used to clear the J-K flip-flops. The $2$-input gate is

A $0$ to $6$ counter consists of $3$ flip flops and a combination circuit of $2$ input gate(s). The combination circuit consists of

A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip flops having a propagation delay of $10 \mathrm{~ns}$ each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then

The circuit in the figure is has two $\text{CMOS NOR}$-gates. This circuit functions as a

For the ring oscillator shown in the figure, the propagation delay of each inverter is $100$ pico sec. What is the fundamental frequency of the oscillator output?

Consider the following two statements : $\text{Statement 1: A}$ stable multivibrator can be used for generating square wave. $\text{Statement 1: B}$ stable multivibrator can be used for storing binary information.

In given figure, the $J$ and $K$ inputs of all the four Flip-Flips are made high. The frequency of the signal at output $Y$ is

A sequential circuit using $D$ Flip-Flop and logic gates is shown in figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is

The ripple counter shown in the given figure is works as a

The figure is shows a mod- $\mathrm{K}$ counter, here $\mathrm{K}$ is equal to

In the figure is $A=1$ and $B=1$, the input $B$ is now replaced by a sequence $101010 \ldots$. , the outputs $x$ and $y$ will be

In a $\text{J-K}$ flip-flip we have $\text{J=Q}$ and $\text{K}=1$. Assuming the flip flop was initially cleared and then clocked for $6$ puleses, the sequence at the $\text{Q}$ output will be

A pulse train can be delayed by a finite number of clock periods using

An $\text{R-S}$ latch is a

A switch-tail ring counter is made by using a single $\text{D}$ flip-flop. The resulting circuit is a

Data can be changed from spatial code to temporal code and vice-versa by using

The initial contents of the $4$-bit serial-in-parallel-out, right-shift, Shift. Register shown in given figure is $0110$. After three clock pulses are applied, the contents of the Shift Register will be