GATE EC Combinatorial Circuits questions

Practise Combinatorial Circuits questions for GATE EC. Explore official PYQs and original topic-wise quizzes, check answers and view available solutions. Free, no sign-in.

20 on this page

SubjectTopicYearType

There are four chips each of

1024\:\text{bytes}

16\:\text{bit}

address bus as shown in the figure below.

RAMs\: 1, 2, 3

4

respectively are mapped to addresses

Y

2-\text{bit}

comparator is logic

1

2-\text{bit}

A

is greater than the

2-\text{bit}

B

. The number of combinations for which the output is logic

1

In the circuit shown

In the sum of products function

f(X,Y,Z)=\sum(2,3,4,5)

, the prime implicants are

The logic function implemented by the circuit below is (ground implies a logic

\text{“0”})

\mathrm{Y}

in the circuit below is always

\text{“1"}

Match the logic gates in Column A with their equivalents in Column B.

\text{F}

1

in the logic circuit shown, the input combination should be

The Boolean function realized by the logic circuit shown is

What are the minimum number of

2

1

multiplexers required to generate a

2

\text{AND}

2

\text{Ex-OR}

The number of product terms in the minimized sum-of-product expression obtained through the following

\text{K}

-map is (where, "

d

" denotes don't care states)

\begin{array}{|c|c|c|c|} \hline 1 & 0 & 0 & 1 \\ \hline 0 & d & 0 & 0 \\ \hline 0 & 0 & d & 1 \\ \hline 1 & 0 & 0 & 1 \\ \hline \end{array}

\frac{\mathrm{I}}{\mathrm{O}}

peripheral device shown in Figure

(b)

below is to be interfaced to an

8085

microprocessor. To select the

\frac{\mathrm{I}}{\mathrm{O}}

\frac{\mathrm{I}}{\mathrm{O}}

\mathrm{D} 4 \mathrm{H}-\mathrm{D} 7 \mathrm{H}

, its chip-select

(\overline{C S})

should be connected to …

\text{P}

in the following figure is stuck-at-

1

f

The Boolean function

f

implemented in the figure using two input multiplexers is

The Boolean expression for the truth table shown is …

What memory address range is

\text{NOT}

represented by chip

\# \; 1

\# \; 2

\text{A}_{0}

\text{A}_{15}

in this figure are the address lines and

\text{CS}

means Chip Select.

Figure given below shows the internal schematic of a

\text{TTL AND-OR}

\text{(AOI)}

gate. For the inputs shown in the given figure, the output

\text{Y}

Given figure is the voltage transfer characteristic of

The minimum number of

2

1

multiplexers required to realize a

4

1

mulitiplexer is

The Boolean expression

\text{AC + B} \overline{\text{C}}

is equivalent to