GATE EC Digital Circuits questions

The minimum number of $2$-input $NAND$ gates required to implement a $2$-input $XOR$ gate is

Following is the K-map of a Boolean function of five variables $P,Q,R,S$ and $X$. The minimum sum-of-product (SOP) expression for the function is

For the circuit shown in the figure, the delays of NOR gates, multiplexers and inverters are $2$ ns, $1.5$ ns and $1$ ns, respectively. If all the inputs $P, Q, R, S$ and $T$ are applied at the same time instant, the maximum propagation delay (in ns) of the circuit is _________

For the circuit shown in the figure, the delay of the bubbled NAND gate is $2\:ns$ and that of the counter is assumed to be zero. If the clock (Clk) frequency is $1\:GHz$, then the counter behaves as a

In an 8085 microprocessor, the shift registers which store the result of an addition and the overflow bit are, respectively

A $16$ Kb ($=16,384$ bits) memory array is designed as a square with an aspect ratio of one (number of rows is equal to the number of columns). The minimum number of address lines needed for the row decoder is ___________

Consider a four bit $D$ to $A$ converter. The analog value corresponding to digital signals of values $0000$ and $0001$ are $0$ V and $0.0625$ V respectively. The analog value (in Volts) corresponding to the digital signal $1111$ is _________

The Boolean expression $F(X,Y,Z) = \overline{X} \: Y \: \overline{Z}+ X \: \overline{Y} \: \overline{Z}+ X \: Y \: \overline{Z} + X \: Y \: Z$ converted into the canonical product of sum (POS) form is

A $3$-input majority gate is defined by the logic function $M(a,b,c)=ab+bc+ca$. Which one of the following gates is represented by the function $M(\overline{M(a,b,c)}, M(a,b,\overline{c}),c)$?

In the figure shown, the output ܻ$Y = AB + \overline{C}\:\:\overline{D}$ is required to be ܻ The gates $G1$ and $G2$ must be, respectively,

In an $8085$ microprocessor, which one of the following instructions changes the content of the accumulator?

A mod-$n$ counter using a synchronous binary up-counter with synchronous clear input is shown in the figure. The value of $n$ is _______.

A function of Boolean variables $X, Y$ and $Z$ is expressed in terms of the min-terms as $$F(X, Y, Z) = \Sigma (1, 2, 5, 6, 7)$$ Which one of the product of sums given below is equal to the function $F(X, Y, Z)?$

The figure shows a binary counter with synchronous clear input. With the decoding logic shown, the counter works as a

A $1$-to-$8$ demultiplexer with data input $D_{in}$ , address inputs $S_{0}, S_{1}, S_{2}$ (with $S_{0}$ as the LSB) and $\overline{Y_{0}}$ to $\overline{Y_{7}}$ as the eight demultiplexed outputs, is to be designed using two $2$-to-$4$ decoders (with enable input $\overline{E}$ and address inputs $A_{0}$ and $A_{1}$) as shown in the …

In the circuit shown, diodes $D_{1}, D_{2}$ and $D_{3}$ are ideal, and the inputs $E_{1} , E_{2}$ and $E_{3}$ are $“0\: V”$ for logic $‘0’$ and $“10\: V”$ for logic $‘1’$. What logic gate does the circuit represent?

Which one of the following $8085$ microprocessor programs correctly calculates the product of two $8$-bit numbers stored in registers $B$ and $C?$

A universal logic gate can implement any Boolean function by connecting sufficient number of them appropriately. Three gates are shown. Which one of the following statements is TRUE?

An SR latch is implemented using TTL gates as shown in the figure. The set and reset pulse inputs are provided using the push-button switches. It is observed that the circuit fails to work as desired. The SR latch can be made functional by changing

Two sequences $x_{1}[n]$ and $x_{2}[n]$ have the same energy. Suppose $x_{1}[n]=\alpha\: 0.5 ^{n}\:u[n],$ where $\alpha$ is a positive real number and $u[n]$is the unit step sequence. Assume ݊$$x_{2}[n]= \begin{cases} \sqrt{1.5}& \text{for } n = 0,1 \\ 0 &\text{otherwise.} \end{cases}$$ Then the value of $\alpha$ is _________.