GATE EC Digital Circuits questions

The noise margin of a $\text{TTL}$ gate is about

The minimum number of $2$-input $\text{NAND}$ gates required to implement the Boolean function $Z=A \bar{B} C$, assiming that $A, B$ and $C$ are available, is

In an $8085 \; \mu \; \mathrm{P}$ system, the $\text{RST}$ instruction will cause an interrupt

The output of the logic gate in the figure is

The inverter $74 \; \mathrm{ALSO} 4$ has the following specifications $$\begin{array}{l} \mathrm{I}_{\text{OH } \max }=-0.4 \mathrm{~mA}, \mathrm{l}_{\text{OLmax }}=8 \mathrm{~mA}, \mathrm{l}_{i H_{\max }}=20 \mathrm{~mA} \text{, } \\ \mathrm{l}_{\text{iLmax }}=-0.1 \mathrm{~mA} \text{, } \end{array}$$ The fan-out based on the above will be

In standard $\text{TTL}$, the 'totem pole' stage refers to

A $2$ bit binary multiplier can be implemented using

Each cell of a Static Random Access Memory contains

The boolean function $\mathrm{A}+\mathrm{BC}$ is a reduced form of

The gate delay of an $\text{NMOS}$ inverter is dominated by charge time rather than discharge time because

In a $\text{J-K}$ flip-flip we have $\text{J=Q}$ and $\text{K}=1$. Assuming the flip flop was initially cleared and then clocked for $6$ puleses, the sequence at the $\text{Q}$ output will be

For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is

A signed integer has been stored in a byte using the $2$'s complement format. We wish to store the same integer in a $16$ bit word. We should

The following insturctions have been executed by an $8085 \; \mu \mathrm{P}$ $\begin{array}{cl}\text{ ADDRESS (HEX) } & \text{ INSTRUCTION } \\ 6010 & \text{ LXI H, 8A } 79 \mathrm{H} \\ 6013 & \text{ MOV A, L } \\ 6015 & \text{ ADDH } \\ 6016 & \text{ DAA } \\ 6017 & \text{ MOV H, A } \\ 6018 & \text{ PCHL }\end{array}$ From …

The decoding circuit shown in the figure is has been used to generate the active low chip select signal for a microprocessor peripheral. (The address lines are designated as $\mathrm{AO}$ to $\mathrm{A} 7$ for $\mathrm{l} / \mathrm{O}$ addresses) The peripheral will correspond to $1 / \mathrm{O}$ addresses in the range

The total number of memory accesses involved (inclusive of the $op$ – code fetch) when an $8085$ processor executes the instruction $\text{LDA}$ $2003$ is

A $12$ – bit $\text{ADC}$ is operating with a $1 \; \mu \; \mathrm{sec}$ clock period and the total conversion time is seen to be $14 \; \mu \;\mathrm{sec}$. The $\text{ADC}$ must be of the

A pulse train can be delayed by a finite number of clock periods using

Schottky clamping is resorted in $\text{TTL}$ gates

The following sequence of instructions are executed by an $8085$ microprocessor: $\begin{matrix} 1000 &LXI & SP &27 \; FF \\ 1000 &CALL & & 1006\\ 1006 &POP \; H & & \end{matrix}$ The contents of the stack pointer $\text{(SP)}$ and the $\text{HL,}$ register pair on completion of execution of these instructions are