GATE CS Computer Arithmetic questions

The following two signed $2$ 's complement numbers (multiplicand M and multiplier Q) are being multiplied using Booth's algorithm: M: $1100110111101101$ and Q: $1010010010101010$ The total number of addition and subtraction operations to be performed is_____________. (Answer in integer)

Consider a carry look ahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in $2$'s complement form. If the decimal value of $A$ is one, the decimal value of $B$ that leads to the longest latency for the sum to stabilize is ___________

A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is $1.2$ microseconds. A $4$-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time …

In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by: $$P_i = A_i \oplus B_i \text{ and }G_i = A_iB_i$$ The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of the look ahead carry adder are given by: …

Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ the carry in, the function that represents the carry generate function when these two numbers are added is:

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using …

Consider the ALU shown below. If the operands are in $2’s$ complement representation, which of the following operations can be performed by suitably setting the control lines $K$ and $C_0$ only (+ and – denote addition and subtraction respectively)?

Consider an array multiplier for multiplying two $n$ bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is

The number of full and half-adders required to add $16$-bit numbers is

The maximum gate delay for any output to appear in an array multiplier for multiplying two $n$ bit numbers is

An N-bit carry lookahead adder, where $N$ is a multiple of $4$, employs ICs $74181$ ($4$ bit ALU) and $74182$ ( $4$ bit carry lookahead generator). The minimum addition time using the best architecture for this adder is

Booth’s algorithm for integer multiplication gives worst performance when the multiplier pattern is