A processor uses bit physical address and bit virtual addresses, with a page frame size of Kbytes. Each page table entry is of size bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows:
- Bits are used to index into the first level page table.
- Bits are used to index into the 2nd level page table.
- Bits are used to index into the 3rd level page table.
- Bits are used as offset within the page.
The number of bits required for addressing the next level page table(or page frame) in the page table entry of the first, second and third level page tables are respectively
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Answer: D
To find the number of bits required to address the next level page table or page frame, we first determine the size and alignment requirements of each level's page table.
1. Size of each level's page table:
- Level 1: Index has bits (bits ). Number of entries = .
Size = . - Level 2: Index has bits (bits ). Number of entries = .
Size = (). - Level 3: Index has bits (bits ). Number of entries = .
Size = (). - Physical Page Frame: Size = ().
2. Addressing bits required in each level:
- First Level PTE points to a Level 2 page table. Since a Level 2 page table is in size, its starting physical address must be aligned to a boundary (the lowest bits are ). Thus, the number of bits required to address it is:
- Second Level PTE points to a Level 3 page table. Since a Level 3 page table is also in size, its starting physical address must be aligned to a boundary (the lowest bits are ). Thus, the number of bits required to address it is:
- Third Level PTE points to a physical page frame. Since a page frame is in size, its starting physical address must be aligned to a boundary (the lowest bits are ). Thus, the number of bits required to address it is:
Therefore, the required bits are 25, 25, and 24 respectively.
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