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Official PYQ · 2014

GATE CS 2014 Set 2 Q55 — Memory Management and Virtual Memory

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Consider the main memory system that consists of 88 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100100 nanoseconds (ns) by the data, address, and control signals. During the same 100100 ns, and for 500500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 11 millisecond is ________
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Answer: 10000

To find the maximum number of stores (write requests) that can be initiated in 1 ms1\text{ ms}, we need to analyze the constraints imposed by both the system bus and the memory modules.

1. System Bus Constraint

  • Each write request occupies the system bus for 100 ns100\text{ ns}.
  • Since only one request can be on the bus at any time, the maximum rate at which requests can be sent over the bus is: Ratebus=1 request100 ns\text{Rate}_{\text{bus}} = \frac{1\text{ request}}{100\text{ ns}}

2. Memory Module Constraint

  • Each memory module takes 100 ns100\text{ ns} (during bus occupation) plus 500 ns500\text{ ns} thereafter to complete a write cycle. Total cycle time per module=100 ns+500 ns=600 ns\text{Total cycle time per module} = 100\text{ ns} + 500\text{ ns} = 600\text{ ns}
  • There are 88 memory modules whose operations can overlap in time.
  • Therefore, the maximum rate at which the 88 modules collectively can process requests is: Ratemodules=8 requests600 ns=1 request75 ns\text{Rate}_{\text{modules}} = \frac{8\text{ requests}}{600\text{ ns}} = \frac{1\text{ request}}{75\text{ ns}}

3. Determining the Bottleneck

The overall maximum rate of initiating write requests is limited by the slower of the two components (the bottleneck):

Maximum Rate=min⁡(Ratebus,Ratemodules)=min⁡(1100 ns,175 ns)=1100 ns\text{Maximum Rate} = \min\left(\text{Rate}_{\text{bus}}, \text{Rate}_{\text{modules}}\right) = \min\left(\frac{1}{100\text{ ns}}, \frac{1}{75\text{ ns}}\right) = \frac{1}{100\text{ ns}}

Since 8×100 ns=800 ns≥600 ns8 \times 100\text{ ns} = 800\text{ ns} \ge 600\text{ ns}, we can continuously cycle through the 88 modules without any module being busy when its turn arrives again. Thus, the system bus is the sole bottleneck.

4. Calculation for 1 Millisecond

Convert 1 millisecond1\text{ millisecond} to nanoseconds:

1 ms=106 ns1\text{ ms} = 10^6\text{ ns}

The maximum number of stores that can be initiated in 1 ms1\text{ ms} is:

Number of stores=106 ns100 ns=10,000\text{Number of stores} = \frac{10^6\text{ ns}}{100\text{ ns}} = 10,000

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