GATE CS 2009 Q34 — Memory Management and Virtual Memory

The correct option is B.

To understand why a multilevel page table is preferred, let's analyze the characteristics of both structures:

1. Page Table Size in Memory: In a single-level page table, the entire page table must reside contiguously in physical memory. For a large virtual address space (e.g., 32-bit or 64-bit), the page table would be extremely large, even if the process uses only a small fraction of its virtual address space (such as just the code, data, heap, and stack segments).
   
   With a multilevel page table, we do not need to allocate the inner page tables for unused regions of the virtual address space. The outer page table entries for these unused regions are simply marked as invalid/null. This drastically reduces the amount of physical memory required to store the page table for a process.
2. Memory Access Time (Option A): Multilevel page tables actually increase the memory access time because translating a virtual address requires accessing memory at each level of the page table (e.g., 2 or 3 memory accesses just for translation) before the actual data can be accessed.
3. TLB Requirement (Option C): The Translation Lookaside Buffer (TLB) is a hardware cache that speeds up address translation. It works independently of the page table structure and does not require a multilevel page table.
4. Page Faults (Option D): The number of page faults is determined by the page replacement policy, the physical memory allocated to the process, and its reference string, not by the organization of the page table.