GATE EC question library
Practise GATE EC Electronics and Communication previous year questions free. Browse by subject, syllabus topic, year and question type, with answers and available solutions.
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In the figure is and are ideal ammeters. If reads reads , then should read.
The two electrical sub network and are connected through three resistors as shown in the figure. The voltage across resistor and resistor are given to be and , respectively. Then voltage across resistor is
A network contains linear resistors and ideal voltage sources. If values of all the resistors are doubled, then the voltage across each resistor is
The built-in potential (Diffusion Potential) in a junction
In a multicavity magnetron, strapping is employed primarily
The beamwidth-between-first null of uniform linear array of equally-spaced (element spacing ), equally-excited antennas is determined by
Two dissimilar antennas having their maximum directivities equal,
Which of the following statements is/are correct?
A transmission line whose characteristic impedance is a pure resistance
Source encoding in a data communication system is done is order to
Coherent demodulation of signal can be effected using
The bit stream is differentially encoded using scheme for transmission. Assuming the reference bit as a and assigning phases of and for ’s and ’s respectively, in the encoded sequence, the transmitted phase sequence becomes
For a random variable following the probability density function, , shown in given figure the mean and the variance are, respectively,
The maximum power efficiency of an modulator is
If represents the Fourier transform of a signal (t) which is real and odd symmetric in time, then
Which of the following signals is/are periodic?
Dual-slope integration type Analog-to-digital converters provide
In an microprocessor system with memory mapped ,
The initial contents of the -bit serial-in-parallel-out, right-shift, Shift. Register shown in given figure is . After three clock pulses are applied, the contents of the Shift Register will be
Given figure shows the circuit of a gate in the Resistor Transistor Logic family. The circuit represents a
