GATE EC Combinatorial Circuits questions

The noise margin of a $\text{TTL}$ gate is about

The minimum number of $2$-input $\text{NAND}$ gates required to implement the Boolean function $Z=A \bar{B} C$, assiming that $A, B$ and $C$ are available, is

The output of the logic gate in the figure is

The inverter $74 \; \mathrm{ALSO} 4$ has the following specifications $$\begin{array}{l} \mathrm{I}_{\text{OH } \max }=-0.4 \mathrm{~mA}, \mathrm{l}_{\text{OLmax }}=8 \mathrm{~mA}, \mathrm{l}_{i H_{\max }}=20 \mathrm{~mA} \text{, } \\ \mathrm{l}_{\text{iLmax }}=-0.1 \mathrm{~mA} \text{, } \end{array}$$ The fan-out based on the above will be

In standard $\text{TTL}$, the 'totem pole' stage refers to

A $2$ bit binary multiplier can be implemented using

The boolean function $\mathrm{A}+\mathrm{BC}$ is a reduced form of

The gate delay of an $\text{NMOS}$ inverter is dominated by charge time rather than discharge time because

For the $\text{NMOS}$ logic gate shown in the figure is the logic function implemented is

The decoding circuit shown in the figure is has been used to generate the active low chip select signal for a microprocessor peripheral. (The address lines are designated as $\mathrm{AO}$ to $\mathrm{A} 7$ for $\mathrm{l} / \mathrm{O}$ addresses) The peripheral will correspond to $1 / \mathrm{O}$ addresses in the range

Schottky clamping is resorted in $\text{TTL}$ gates

The minimum number of $\text{NAND}$ gates required to implement the Boolean function $\mathrm{A}+\mathrm{A} \overline{\mathrm{B}}+\mathrm{A} \overline{\mathrm{B}} \mathrm{C}$, is equal to

The output of the circuit in the figure is equal to

A $\text{PLA}$ can be used

The output of a logic gate is ‘$1$’ when all its inputs are at logic ‘$0$’. Then gate is either

Given figure shows the circuit of a gate in the Resistor Transistor Logic $\text{(RTL)}$ family. The circuit represents a

The logic realized by the circuit shown in given figure is