Official PYQ · 2019Set 1 · Q13MCQ1 mark

GATE EC 2019 Set 1 Q13 — Electronic Devices

A standard CMOS inverter is designed with equal rise and fall times $(\beta_{n}=\beta_{p}).$ If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin $NM_{L}$ and the HIGH noise margin $NM_{H}$ ?

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Published 10 Oct 2026

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