In complement addition, overflow
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Answer: B
In 's complement representation, overflow occurs when the result of an arithmetic operation falls outside the representable range of the given number of bits.
Let's analyze the options:
- Option B is correct: When adding a positive number and a negative number, the magnitude of the sum is always strictly less than or equal to the magnitude of the larger operand. Consequently, the result is guaranteed to lie within the representable range, meaning overflow can never occur.
- Option A is incorrect: A carry out of the sign bit does not necessarily indicate an overflow. For example, in -bit 's complement, adding () and () yields () with a carry-out of from the sign bit, but no overflow has occurred.
- Option C is incorrect: Overflow is flagged when the carry into the sign bit () and the carry out of the sign bit () differ (i.e., ). If they match, there is no overflow.
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