GATE CS 2015 Set 1 Q8 — Intermediate Code Generation

In a computer architecture utilizing a three-address instruction format, a typical instruction has the structure:

$$\text{op} \quad \text{destination}, \quad \text{source}_1, \quad \text{source}_2$$

Each of the three address fields in this format must explicitly specify the location of an operand or the destination. Depending on the specific ISA (Instruction Set Architecture):

• S1 (A memory operand): In memory-to-memory architectures, any of the address fields can specify a memory address.
• S2 (A processor register): In register-to-register (load-store) or register-memory architectures, the address fields can specify general-purpose processor registers.
• S3 (An implied accumulator register): By definition, an implied register is implicit to the opcode and does not require an explicit address field in the instruction format (as seen in one-address accumulator-based architectures).

Therefore, each address field can be used to specify either a memory operand ($S1$) or a processor register ($S2$).

Thus, the correct option is A.