GATE CS 2018 Q9 — System Calls

When a device controller issues an interrupt while a process $L$ is executing, the CPU handles it in a structured sequence to ensure that the state of process $L$ is preserved and can be resumed seamlessly later. The step-by-step sequence is as follows:

1. Q. The processor finishes the execution of the current instruction: The CPU checks for pending interrupts only at the end of an instruction cycle. It must complete the currently executing instruction first.
2. P. The processor pushes the process status of $L$ onto the control stack: Before servicing the interrupt, the CPU saves the state of the interrupted process $L$ (such as the program counter, processor status word, and registers) onto the control stack so it can resume later.
3. T. The processor loads the new PC value based on the interrupt: The CPU fetches the address of the corresponding Interrupt Service Routine (ISR) from the interrupt vector table and loads it into the Program Counter (PC).
4. R. The processor executes the interrupt service routine: The CPU executes the instructions of the ISR to handle the device request.
5. S. The processor pops the process status of $L$ from the control stack: Once the ISR completes, the CPU restores the saved state of process $L$ from the control stack to resume its execution from where it was interrupted.

Thus, the correct sequence of events is Q → P → T → R → S (QPTRS).